Experiences with implementing common mathematical operations using field programmable gate arrays

Many computationally intensive scientific applications involve repetitive floating point operations other than addition and multiplication which may present a significant performance bottleneck due to the relatively large latency or low throughput involved in executing such arithmetic primitives on commod- ity processors. A promising alternative is to execute such primitives on Field Programmable Gate Array (FPGA) hardware acting as an application-specific custom co-processor in a high performance reconfig- urable computing platform. The use of FPGAs can provide advantages such as fine-grain parallelism but issues relating to code development in a hardware description language and efficient data transfer to and from the FPGA chip can present significant application development challenges. In this paper, we discuss our practical experiences in developing a selection of floating point hardware designs to be implemented using FPGAs. Our designs include some basic mathemati cal library functions which can be implemented for user defined precisions suitable for novel applications requiring non-standard floating point represen- tation. We discuss the details of our designs along with results from performance and accuracy analysis tests.

Solving tri-diagonal linear systems using field programmable gate arrays

In this paper, we present the outcomes of a project on the exploration of the use of Field Programmable Gate Arrays(FPGAs) as co-processors for scientific computation. We designed a custom circuit for the pipelined solving of multiple tri-diagonal linear systems. The design is well suited for applications that require many independent tri diagonal system solves, such as finite difference methods for solving PDEs or applications utilising cubic spline interpolation. The selected solver algorithm was the Tri Diagonal Matrix Algorithm (TDMA or Thomas Algorithm). Our solver supports user specified precision thought the use of a custom floating point VHDL library supporting addition, subtraction, multiplication and division. The variable precision TDMA solver was tested for correctness in simulation mode. The TDMA pipeline was tested successfully in hardware using a simplified solver model. The details of implementation, the limitations, and future work are also discussed.

Solving tri-diagonal linear systems using field programmable gate arrays

In this paper, we present the outcomes of a project on the exploration of the use of Field Programmable Gate Arrays (FPGAs) as co-processors for scientific computation. We designed a custom circuit for the pipelined solving of multiple tri-diagonal linear systems. The design is well suited for applications that require many independent tri-diagonal system solves, such as finite difference methods for solving PDEs or applications utilising cubic spline interpolation. The selected solver algorithm was the Tri-Diagonal Matrix Algorithm (TDMA or Thomas Algorithm). Our solver supports user specified precision thought the use of a custom floating point VHDL library supporting addition, subtraction, multiplication and division. The variable precision TDMA solver was tested for correctness in simulation mode. The TDMA pipeline was tested successfully in hardware using a simplified solver model. The details of implementation, the limitations, and future work are also discussed.

Assessing eco-environmental performance of agricultural production in OECD countries : combination of soil surface, soil system and farm gate methods of nutrient auditing

Nitrogen balance is increasingly used as an indicator of the environmental performance of agricultural sector in national, international, and global contexts. There are three main methods of accounting the national nitrogen balance: farm gate, soil surface, and soil system. OECD (2008) recently reported the nitrogen and phosphorus balances for member countries for the 1985 - 2004 period using the soil surface method. The farm gate and soil system methods were also used in some international projects. Some studies have provided the comparison among these methods and the conclusion is mixed. The motivation of this present paper was to combine these three methods to provide a more detailed auditing of the nitrogen balance and flows for national agricultural production. In addition, the present paper also provided a new strategy of using reliable international and national data sources to calculate nitrogen balance using the farm gate method. The empirical study focused on the nitrogen balance of OECD countries for the period from 1985 to 2003. The N surplus sent to the total environment of OECD surged dramatically in early 1980s, gradually decreased during 1990s but exhibited an increasing trends in early 2000s. The overall N efficiency however fluctuated without a clear increasing trend. The eco-environmental ranking shows that Australia and Ireland were the worst while Korea and Greece were the best.

Regulating bereavement : inquests, family pressure and the gate keeping of suicide statistics

This study of English Coronial practice raises a number of questions, not only regarding state investigations of suicide, but also of the role of the Coroner itself. Following observations at over 20 inquests into possible suicides, and in-depth interviews with six Coroners, three main issue emerged: first, there exists considerable slippage between different Coroners over which deaths are likely to be classified as suicide; second, the high standard of proof required, and immense pressure faced by Coroners from family members at inquest to reach any verdict other than suicide, can significantly depress likely suicide rates; and finally, Coroners feel no professional obligation, either individually or collectively, to contribute to the production of consistent and useful social data regarding suicide—arguably rendering comparative suicide statistics relatively worthless. These issues lead, ultimately, to a more important question about the role we expect Coroners to play within social governance, and within an effective, contemporary democracy.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Logic-gate devices based on printed polymer semiconducting nanostripes

The applications of organic semiconductors in complex circuitry such as printed CMOS-like logic circuits demand miniaturization of the active structures to the submicrometric and nanoscale level while enhancing or at least preserving the charge transport properties upon processing. Here, we addressed this issue by using a wet lithographic technique, which exploits and enhances the molecular order in polymers by spatial confinement, to fabricate ambipolar organic field effect transistors and inverter circuits based on nanostructured single component ambipolar polymeric semiconductor. In our devices, the current flows through a precisely defined array of nanostripes made of a highly ordered diketopyrrolopyrrole-benzothiadiazole copolymer with high charge carrier mobility (1.45 cm2 V-1 s-1 for electrons and 0.70 cm2 V-1 s-1 for holes). Finally, we demonstrated the functionality of the ambipolar nanostripe transistors by assembling them into an inverter circuit that exhibits a gain (105) comparable to inverters based on single crystal semiconductors.

High mobility top-gate and dual-gate polymer thin-film transistors based on diketopyrrolopyrrole-naphthalene copolymer

In this letter, the performance characteristics of top-gate and dual-gate thin-film transistors (TFTs) with active semiconductor layers consisting of diketopyrrolopyrrole-naphthalene copolymer are described. Optimized top-gate TFTs possess mobilities of up to 1 cm 2 /V s with low contact resistance and reduced hysteresis in air. Dual-gate devices possess higher drive currents as well as improved subthreshold and above threshold characteristics compared to single-gate devices. We also describe the reasons that dual-gate devices result in improved performance. The good stability of this polymer combined with their promising electrical properties make this material a very promising semiconductor for printable electronics.

Charge-carrier velocity distributions in high-mobility polymer dual-gate thin-film transistors

We report charge-carrier velocity distributions in high-mobility polymer thin-film transistors (PTFTs) employing a dual-gate configuration. Our time-domain measurements of dual-gate PTFTs indicate higher effective mobility as well as fewer low-velocity carriers than in single-gate operation. Such nonquasi-static (NQS) measurements support and clarify the previously reported results of improved device performance in dual-gate devices by various groups. We believe that this letter demonstrates the utility of NQS measurements in studying charge-carrier transport in dual-gate thin-film transistors.

Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Improved performance in diketopyrrolopyrrole-based transistors with bilayer gate dielectrics

There has been significant progress in the past 2 decades in the field of organic and polymer thin-film transistors. In this paper, we report a combination of stable materials, device architecture, and process conditions that resulted in a patterned gate, small channel length (<5 μm) device that possesses a scaled field-induced conductivity in air that is higher than any organic/polymer transistor reported thus far. The operating voltage is below 10 V; the on-off ratio is high; and the active materials are solution-processable. The semiconducting polymer is a new donor-acceptor polymer with furan-substituted diketopyrrolopyrrole and thienyl-vinylene-thienyl building blocks in the conjugated backbone. One of the major striking features of our work is that the patterned-gate device architecture is suitable for practical applications. We also propose a figure of merit to meaningfully compare polymer/organic transistor performance that takes into account mobility and operating voltage. With this figure of merit, we compare leading organic and polymer transistors that have been hitherto reported. The material and device architecture have shown very high mobility and low operating voltage for such short channel length (below 5 μm) organic/polymer transistors.

The influence of atmospheric conditions on the leakage current of ceramic insulators on the Colombian Caribbean coast

The contamination of electrical insulators is one of the major contributors to the risk of operation outages in electrical substations, especially in coastal zones with high salinity levels and atmospheric pollution. By using the measurement of leakage-currents, which is one of the main indicators of contamination in insulators, this work seeks to the determine the correlation with climatic variables, such as ambient temperature, relative humidity, solar irradiance, atmospheric pressure, and wind speed and direction. The results obtained provide an input to the behaviour of the leakage current under atmospheric conditions that are particular to the Caribbean coast of Colombia. Spearman’s rank correlation coefficients and principal component analysis are utilised to determine the significant relationships among the different variables under consideration. The necessary information for the study was obtained via historical databases of both atmospheric variables and the leakage current measured in over a period of one year in a 220-kV potential transformer insulator. We identified the influencing factors of temperature, humidity, radiation, wind speed and direction on the magnitude of the leakage current as the most relevant.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.