Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders

Run-time interoperability between different applications based on H.264/AVC is an emerging need in networked infotainment, where media delivery must match the desired resolution and quality of the end terminals. In this paper, we describe the architecture and design of a polymorphic ASIC to support this. The H.264 decoding flow is partitioned into modules, such that the polymorphic ASIC meets the design goals of low-power, low-area, high flexibility, high throughput and fast interoperability between different profiles and levels of H.264. We demonstrate the idea with a multi-mode decoder that can decode baseline, main and high profile H.264 streams and can interoperate at run.time across these profiles. The decoder is capable of processing frame sizes of up to 1024 times 768 at 30 fps. The design synthesized with UMC 0.13 mum technology, occupies 250 k gates and runs at 100 MHz.

DIY/DIWO media architecture: The InstaBooth

Building on previous discourse regarding the ability of media architecture to be more open and accessible for the purposes of community engagement (Caldwell & Foth, 2014), this chapter explores a particular case study that was designed, constructed and implemented with the intention of allowing city users to participate in the development and creation of media architecture, the InstaBooth. In this chapter, we first explore DIY (do it yourself) and DIWO (do it with others) phenomena to examine what motivates the DIY cultures, communities, and practices. Secondly, in this chapter, we define and discuss our implementation of a DIY / DIWO media architecture example, the InstaBooth. The InstaBooth project pro-vides an opportunity to question the effectiveness of a DIY driven media architec-ture artefact to see to what extent it impacts on the experience of its users and for what benefit.

Scopophobia/Scopophilia: electric light and the anxiety of the gaze in postwar American architecture

In the years of reconstruction and economic boom that followed the Second World War, the domestic sphere encountered new expectations regarding social behaviour, modes of living, and forms of dwelling. This book brings together an international group of scholars from architecture, design, urban planning, and interior design to reappraise mid-twentieth century modern life, offering a timely reassessment of culture and the economic and political effects on civilian life. This collection contains essays that examine the material of art, objects, and spaces in the context of practices of dwelling over the long span of the postwar period. It asks what role material objects, interior spaces, and architecture played in quelling or fanning the anxieties of modernism’s ordinary denizens, and how this role informs their legacy today. Table of Contents [Book] Introduction Robin Schuldenfrei Part 1: Psychological Constructions: Anxiety of Isolation and Exposure 1. Taking Comfort in the Age of Anxiety: Eero Saarinen’s Womb Chair Cammie McAtee 2. The Future is Possibly Past: The Anxious Spaces of Gaetano Pesce Jane Pavitt 3. Scopophobia/Scopophilia: Electric Light and the Anxiety of the Gaze in American Postwar Domestic Architecture Margaret Petty Part 2: Ideological Objects: Design and Representation 4. The Allegory of the Socialist Lifestyle: The Czechoslovak Pavilion at the Brussels Expo, its Gold Medal and the Politburo Ana Miljacki 5. Assimilating Unease: Moholy-Nagy and the Wartime-Postwar Bauhaus in Chicago Robin Schuldenfrei 6. The Anxieties of Autonomy: Peter Eisenman from Cambridge to House VI Sean Keller Part 3: Societies of Consumers: Materialist Ideologies and Postwar Goods 7. "But a home is not a laboratory": The Anxieties of Designing for the Socialist Home in the German Democratic Republic 1950—1965 Katharina Pfützner 8. Architect-designed Interiors for a Culturally Progressive Upper-Middle Class: The Implicit Political Presence of Knoll International in Belgium Fredie Floré 9. Domestic Environment: Italian Neo-Avant-Garde Design and the Politics of Post-Materialism Mary Louise Lobsinger Part 4: Class Concerns and Conflict: Dwelling and Politics 10. Dirt and Disorder: Taste and Anxiety in the Working Class Home Christine Atha 11. Upper West Side Stories: Race, Liberalism, and Narratives of Urban Renewal in Postwar New York Jennifer Hock 12. Pawns or Prophets? Postwar Architects and Utopian Designs for Southern Italy Anne Parmly Toxey. Coda: From Homelessness to Homelessness David Crowley

Heritability of the network architecture of intrinsic brain functional connectivity

The brain's functional network exhibits many features facilitating functional specialization, integration, and robustness to attack. Using graph theory to characterize brain networks, studies demonstrate their small-world, modular, and "rich-club" properties, with deviations reported in many common neuropathological conditions. Here we estimate the heritability of five widely used graph theoretical metrics (mean clustering coefficient (γ), modularity (Q), rich-club coefficient (ϕnorm), global efficiency (λ), small-worldness (σ)) over a range of connection densities (k=5-25%) in a large cohort of twins (N=592, 84 MZ and 89 DZ twin pairs, 246 single twins, age 23±2.5). We also considered the effects of global signal regression (GSR). We found that the graph metrics were moderately influenced by genetic factors h2 (γ=47-59%, Q=38-59%, ϕnorm=0-29%, λ=52-64%, σ=51-59%) at lower connection densities (≤15%), and when global signal regression was implemented, heritability estimates decreased substantially h2 (γ=0-26%, Q=0-28%, ϕnorm=0%, λ=23-30%, σ=0-27%). Distinct network features were phenotypically correlated (|r|=0.15-0.81), and γ, Q, and λ were found to be influenced by overlapping genetic factors. Our findings suggest that these metrics may be potential endophenotypes for psychiatric disease and suitable for genetic association studies, but that genetic effects must be interpreted with respect to methodological choices.

From the {Cu(μ2-S)N}4 butterfly architecture to the {Cu(μ3-S)N}12 double wheel

Copper(I) complexes with {Cu(μ2-S)N}4 and {Cu(μ3-S)N}12 core portions of butterfly-shaped or double wheel architectures have been isolated in the reaction of Cu(I) with the Schiff base ligand C6H4(CHNC6H4S)2, aiso-abtâ, under different conditions. View the MathML source containing the tetranuclear electroneutral complex View the MathML source is formed by the reaction of CuI in acetonitrilic solution and recrystallization from DMF, whereas View the MathML source containing dodecanuclear View the MathML source wheels is accessible starting from CuBF4. Complexes 2 and 4 represent the first examples of cyclic complexes with the same overall stoichiometry but different ring sizes. The ligand induces two different coordination environments around copper(I) by switching between μ2- and μ3-sulfur bridging modes.

Blurring the physical boundaries of the city: Media architecture and urban informatics for community engagement

Architecture focuses on designing built environments in response to society’s needs, reflecting culture through materials and forms. The physical boundaries of the city have become blurred through the integration of digital media, connecting the physical environment with the digital. In the recent past the future was imagined as highly technological; 1982 Ridley Scott’s Blade Runner is set in 2019 and introduces a world where supersized screens inject advertisements in the cluttered urban space. Now, in 2015 screens are central to everyday life, but in a completely different way in respect to what had been imagined. Through ubiquitous computing and social media, information is abundant. Digital technologies have changed the way people relate to cities supporting discussion on multiple levels, allowing citizens to be more vocal than ever before. We question how architects can use the affordances of urban informatics to obtain and navigate useful social information to inform design. This chapter investigates different approaches to engage communities in the debate on cities, in particular it aims to capture citizens’ opinions on the use and design of public places. Physical and digital discussions have been initiated to capture citizens’ opinions on the use and design of public places. In addition to traditional consultation methods, Web 2.0 platforms, urban screens, and mobile apps are used in the context of Brisbane, Australia to explore contemporary strategies of engagement (Gray 2014).

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.