A new method based on the construction of hypothetical symmetrical networks for fixture calibration in network analyzers

At least three known standards are normally required for the full two-port test fixture calibration in vector network analyzers (VNA). In this paper, a calibration procedure using only one standard, based on establishing two hypothetical symmetrical fixtures using triple-through method, is shown. The results using the calibrating method to subtract the influence of fixtures are in accord with the directly measured data of the device-under-test (DUT) without the fixtures very well, which shows that the proposed method is very simple and accurate.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Ultra-narrow dual-channel filter based on symmetrical sampled fibre Bragg grating

A kind of ultra-narrow dual-channel filter is proposed in principle and demonstrated experimentally. This filter is designed by means of two sampled fibre Bragg gratings (SFBGs), where one is periodic 0-pi sampling and the other is symmetrical spatial sampling. The former can create two stopbands in the transmission spectra and the latter can produce two ultra-riarrow passbands. Our filter has the 3-dB bandwidth of about 1 pm, whose value is two orders of magnitude less than the bandwidth of the traditional SFBG filters. The proposed filter has a merit that the channel spacing remains unchanged when tuning the filter.

A novel dual-wavelength DFB fiber laser based on symmetrical FBG structure

A novel grating structure is proposed and demonstrated to obtain stable dual-wavelength (DW) distributed-feedback (DFB) fiber lasers at room temperature. The proposed grating is based on a symmetrical structure, where one half is periodically sampled by "0"-to-"pi" period and the other half is done by "pi"-to-"0" period. This structure can create two separated resonance cavities and hence achieve the stable DW lasing operation. By fabricating the proposed grating on a piece of Er: Yb-codoped fiber, we experimentally obtain a stable DW-DFB fiber laser with wavelength spacing of similar to 440 pm at room temperature.

Exact description of a cylindrically symmetrical complex-argument Laguerre-Gauss beam

Based on the perturbative series representation of a complex-source-point spherical wave an expression for cylindrically symmetrical complex-argument Laguerre-Gauss beams of radial order n is derived. This description acquires the accuracy up to any order of diffraction angle, and its first three corrected terms are in accordance with those given by Seshadri [Opt. Lett. 27, 1872 (2002)] based on the virtual source method. Numerical results show that on the beam axis the number of orders of nonvanishing nonparaxial corrections is equal to n. Meanwhile a higher radial mode number n leads to a smaller convergent domain of radius. (C) 2008 Optical Society of America.

Sagnac棱镜角公差与干涉光谱仪光谱分辨率的关系分析

根据干涉成像光谱仪光谱分辨率对角向差的要求，通过对实体Sagnac干涉仪结构和光路 进行分析，从三个相互垂直的方向出发，研究了光谱分辨率和棱镜角公差之间存在的关系；并推导 了满足光谱仪光谱分辨率要求的实体Sagnac干涉棱镜的角公差公式；用实例说明了关系式的应用 方法，如果不考虑棱镜变形引起的色散及棱镜的面型误差和付氏镜的残余像差的影响，而只考虑棱 镜的角误差对光谱分辨率的影响，则通常情况下干涉棱镜的角公差要求较严，约2O”以内．

Sagnac滤波器的自动补偿

提出了对双折射光纤Sagnac滤波器的自动补偿方案,将其粘贴在大热膨胀系数的基底材料上,使双折射光纤Sagnac滤波器自动补偿其光谱波长对温度产生的漂移.经过封装后双折射光纤Sagnac滤波器波长对温度的灵敏度降低到0.059nm/℃,是未封装前的0.04倍.这种方法简单可行,并在一定程度上解决了双折射Sagnac滤波器温度敏感的问题,使器件的实用化进程向前迈进了一步.