Triggers per attività di test su fascio di particelle. Realizzazione di un progetto in VHDL e sintetizzazione su FPGA

Progettazione e realizzazione di un dispositivo elettronico con lo scopo di coordinare e sincronizzare la presa dati del beam test del LUCID (CERN, luglio 2009) e tener traccia di tali eventi. Il circuito è stato progettato in linguaggio VHDL, simulato con il programma ModelSim, sintetizzato con il programma Quartus e implementato su un FPGA Cyclone residente su scheda di tipo VME 6U della CAEN. Infine la scheda è stata testata in laboratorio (verificandone il corretto funzionamento) assieme all'intero sistema di presa dati, e confermata per il beam test del LUCID.

Cooperative and reconfigurable telecommunication systems based on FPGA

This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.

Sviluppo di un modulo VHDL per interfacciamento Ethernet-FPGA in applicazioni di high throughput screening

In molti settori della ricerca in campo biologico e biomedico si fa ricorso a tecniche di High Throughput Screening (HTS), tra cui studio dei canali ionici. In questo campo si studia la conduzione di ioni attraverso una membrana cellulare durante fenomeni che durano solo alcuni millisecondi. Allo scopo sono solitamente usati sensori e convertitori A/D ad elevata velocità insieme ad opportune interfacce di comunicazione, ad elevato bit-rate e latenza ridotta. In questa tesi viene descritta l'implementazione di un modulo VHDL per la trasmissione di dati digitali provenienti da un sistema HTS attraverso un controller di rete integrato dotato di un'interfaccia di tipo Ethernet, individuando le possibili ottimizzazioni specifiche per l'applicazione di interesse.

Design and implementation of a novel multi-constellation FPGA-based dual frequency GNSS receiver for space applications

The PhD activity described in the document is part of the Microsatellite and Microsystem Laboratory of the II Faculty of Engineering, University of Bologna. The main objective is the design and development of a GNSS receiver for the orbit determination of microsatellites in low earth orbit. The development starts from the electronic design and goes up to the implementation of the navigation algorithms, covering all the aspects that are involved in this type of applications. The use of GPS receivers for orbit determination is a consolidated application used in many space missions, but the development of the new GNSS system within few years, such as the European Galileo, the Chinese COMPASS and the Russian modernized GLONASS, proposes new challenges and offers new opportunities to increase the orbit determination performances. The evaluation of improvements coming from the new systems together with the implementation of a receiver that is compatible with at least one of the new systems, are the main activities of the PhD. The activities can be divided in three section: receiver requirements definition and prototype implementation, design and analysis of the GNSS signal tracking algorithms, and design and analysis of the navigation algorithms. The receiver prototype is based on a Virtex FPGA by Xilinx, and includes a PowerPC processor. The architecture follows the software defined radio paradigm, so most of signal processing is performed in software while only what is strictly necessary is done in hardware. The tracking algorithms are implemented as a combination of Phase Locked Loop and Frequency Locked Loop for the carrier, and Delay Locked Loop with variable bandwidth for the code. The navigation algorithm is based on the extended Kalman filter and includes an accurate LEO orbit model.

Dispositivi FPGA di ultima generazione: analisi e confronto

Questa tesi si prefissa l’obiettivo di analizzare l'evoluzione dei sistemi FPGA nel corso degli ultimi anni, evidenziando le novità e gli aspetti tecnici più significativi che ogni famiglia ha introdotto. Il primo capitolo avrà il compito di mostrare l’architettura ed il funzionamento generale di un FPGA, cercando di illustrarne le principali caratteristiche. Il secondo capitolo introdurrà i dispositivi FPGA Xilinx e mostrerà le caratteristiche tecniche dei principali dispositivi prodotto dall'azienda. Il terzo capitolo mostrerà invece le caratteristiche tecniche degli FPGA più recenti prodotti da Altera. Il quarto ed ultimo capitolo, invece, metterà a confronto alcuni parametri fondamentali dei dispositivi descritti nell'elaborato.

Ottimizzazione di protocolli di trasmissione dati tramite interfaccia usb implementati su fpga

La maggior parte dei moderni dispositivi e macchinari, sia ad uso civile che industriale, utilizzano sistemi elettronici che ne supervisionano e ne controllano il funzionamento. All’ interno di questi apparati è quasi certamente impiegato un sistema di controllo digitale che svolge, anche grazie alle potenzialità oggi raggiunte, compiti che fino a non troppi anni or sono erano dominio dell’ elettronica analogica, si pensi ad esempio ai DSP (Digital Signal Processor) oggi impiegati nei sistemi di telecomunicazione. Nonostante l'elevata potenza di calcolo raggiunta dagli odierni microprocessori/microcontrollori/DSP dedicati alle applicazioni embedded, quando è necessario eseguire elaborazioni complesse, time-critical, dovendo razionalizzare e ottimizzare le risorse a disposizione, come ad esempio spazio consumo e costi, la scelta ricade inevitabilmente sui dispositivi FPGA. I dispositivi FPGA, acronimo di Field Programmable Gate Array, sono circuiti integrati a larga scala d’integrazione (VLSI, Very Large Scale of Integration) che possono essere configurati via software dopo la produzione. Si differenziano dai microprocessori poiché essi non eseguono un software, scritto ad esempio in linguaggio assembly oppure in linguaggio C. Sono invece dotati di risorse hardware generiche e configurabili (denominate Configurable Logic Block oppure Logic Array Block, a seconda del produttore del dispositivo) che per mezzo di un opportuno linguaggio, detto di descrizione hardware (HDL, Hardware Description Language) vengono interconnesse in modo da costituire circuiti logici digitali. In questo modo, è possibile far assumere a questi dispositivi funzionalità logiche qualsiasi, non previste in origine dal progettista del circuito integrato ma realizzabili grazie alle strutture programmabili in esso presenti.

Implementazione su fpga di un pre-distorsore digitale a banda larga per sistemi a microonde di backhaul

The development of next generation microwave technology for backhauling systems is driven by an increasing capacity demand. In order to provide higher data rates and throughputs over a point-to-point link, a cost-effective performance improvement is enabled by an enhanced energy-efficiency of the transmit power amplification stage, whereas a combination of spectrally efficient modulation formats and wider bandwidths is supported by amplifiers that fulfil strict constraints in terms of linearity. An optimal trade-off between these conflicting requirements can be achieved by resorting to flexible digital signal processing techniques at baseband. In such a scenario, the adaptive digital pre-distortion is a well-known linearization method, that comes up to be a potentially widely-used solution since it can be easily integrated into base stations. Its operation can effectively compensate for the inter-modulation distortion introduced by the power amplifier, keeping up with the frequency-dependent time-varying behaviour of the relative nonlinear characteristic. In particular, the impact of the memory effects become more relevant and their equalisation become more challenging as the input discrete signal feature a wider bandwidth and a faster envelope to pre-distort. This thesis project involves the research, design and simulation a pre-distorter implementation at RTL based on a novel polyphase architecture, which makes it capable of operating over very wideband signals at a sampling rate that complies with the actual available clock speed of current digital devices. The motivation behind this structure is to carry out a feasible pre-distortion for the multi-band spectrally efficient complex signals carrying multiple channels that are going to be transmitted in near future high capacity and reliability microwave backhaul links.

Performance Modeling Of Reconfigurable Distributed Systems Based On The Opensparc Fpga Board And The Sirc Communication Framewor

This thesis explores system performance for reconfigurable distributed systems and provides an analytical model for determining throughput of theoretical systems based on the OpenSPARC FPGA Board and the SIRC Communication Framework. This model was developed by studying a small set of variables that together determine a system¿s throughput. The importance of this model is in assisting system designers to make decisions as to whether or not to commit to designing a reconfigurable distributed system based on the estimated performance and hardware costs. Because custom hardware design and distributed system design are both time consuming and costly, it is important for designers to make decisions regarding system feasibility early in the development cycle. Based on experimental data the model presented in this paper shows a close fit with less than 10% experimental error on average. The model is limited to a certain range of problems, but it can still be used given those limitations and also provides a foundation for further development of modeling reconfigurable distributed systems.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.

Design and Development of an FPGA-based Distributed Computing Processing Platform

This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using a distributed system of field-programmable gate array (FPGA) boards. The software framework providesusers with the ability to easily develop applications that exploit the processing power of FPGAs while the hardware core manager framework gives users the ability to configure and interact with multiple FPGA boards and/or hardware cores. This thesis describes the design and development of these frameworks and analyzes the performance of a system that was constructed using the frameworks. The performance analysis included measuring the effect of incorporating additional hardware components into the system and comparing the system to a software-only implementation. This work draws conclusions based on the provided results of the performance analysis and offers suggestions for future work.

DESIGN AND IMPLEMENT DYNAMIC PROGRAMMING BASED DISCRETE POWER LEVEL SMART HOME SCHEDULING USING FPGA

With the development and capabilities of the Smart Home system, people today are entering an era in which household appliances are no longer just controlled by people, but also operated by a Smart System. This results in a more efficient, convenient, comfortable, and environmentally friendly living environment. A critical part of the Smart Home system is Home Automation, which means that there is a Micro-Controller Unit (MCU) to control all the household appliances and schedule their operating times. This reduces electricity bills by shifting amounts of power consumption from the on-peak hour consumption to the off-peak hour consumption, in terms of different “hour price”. In this paper, we propose an algorithm for scheduling multi-user power consumption and implement it on an FPGA board, using it as the MCU. This algorithm for discrete power level tasks scheduling is based on dynamic programming, which could find a scheduling solution close to the optimal one. We chose FPGA as our system’s controller because FPGA has low complexity, parallel processing capability, a large amount of I/O interface for further development and is programmable on both software and hardware. In conclusion, it costs little time running on FPGA board and the solution obtained is good enough for the consumers.

Power Measurement Methodology for FPGA Devices

The efficiency of power optimization tools depends on information on design power provided by the power estimation models. Power models targeting different power groups can enable fast identification of the most power consuming parts of design and their properties. The accuracy of these estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precision is achieved by using physical onboard measurements. In this paper, we present a measurement methodology that is primarily aimed at calibrating and validating high-level dynamic power estimation models. The measurements have been carefully designed to enable the separation of the interconnect power from the logic power and the power of the clock circuitry, so that each of these power groups can be used for the corresponding model validation. The standard measurement uncertainty is lower than 2% of the measured value even with a very small number of repeated measurements. Additionally, the accuracy of a commercial low-level power estimation tool has been also assessed for comparison purposes. The results indicate that the tool is not suitable for power estimation of data path-oriented designs.