Oscillations by minimal bacterial suicide circuits reveal hidden facets of host-circuit physiology.

Synthetic biology seeks to enable programmed control of cellular behavior though engineered biological systems. These systems typically consist of synthetic circuits that function inside, and interact with, complex host cells possessing pre-existing metabolic and regulatory networks. Nevertheless, while designing systems, a simple well-defined interface between the synthetic gene circuit and the host is frequently assumed. We describe the generation of robust but unexpected oscillations in the densities of bacterium Escherichia coli populations by simple synthetic suicide circuits containing quorum components and a lysis gene. Contrary to design expectations, oscillations required neither the quorum sensing genes (luxR and luxI) nor known regulatory elements in the P(luxI) promoter. Instead, oscillations were likely due to density-dependent plasmid amplification that established a population-level negative feedback. A mathematical model based on this mechanism captures the key characteristics of oscillations, and model predictions regarding perturbations to plasmid amplification were experimentally validated. Our results underscore the importance of plasmid copy number and potential impact of "hidden interactions" on the behavior of engineered gene circuits - a major challenge for standardizing biological parts. As synthetic biology grows as a discipline, increasing value may be derived from tools that enable the assessment of parts in their final context.

Neuroepithelial circuit formed by innervation of sensory enteroendocrine cells.

Satiety and other core physiological functions are modulated by sensory signals arising from the surface of the gut. Luminal nutrients and bacteria stimulate epithelial biosensors called enteroendocrine cells. Despite being electrically excitable, enteroendocrine cells are generally thought to communicate indirectly with nerves through hormone secretion and not through direct cell-nerve contact. However, we recently uncovered in intestinal enteroendocrine cells a cytoplasmic process that we named neuropod. Here, we determined that neuropods provide a direct connection between enteroendocrine cells and neurons innervating the small intestine and colon. Using cell-specific transgenic mice to study neural circuits, we found that enteroendocrine cells have the necessary elements for neurotransmission, including expression of genes that encode pre-, post-, and transsynaptic proteins. This neuroepithelial circuit was reconstituted in vitro by coculturing single enteroendocrine cells with sensory neurons. We used a monosynaptic rabies virus to define the circuit's functional connectivity in vivo and determined that delivery of this neurotropic virus into the colon lumen resulted in the infection of mucosal nerves through enteroendocrine cells. This neuroepithelial circuit can serve as both a sensory conduit for food and gut microbes to interact with the nervous system and a portal for viruses to enter the enteric and central nervous systems.

Computational modeling techniques for reliability of electronic components on printed circuit boards

This paper describes modeling technology and its use in providing data governing the assembly and subsequent reliability of electronic chip components on printed circuit boards (PCBs). Products, such as mobile phones, camcorders, intelligent displays, etc., are changing at a tremendous rate where newer technologies are being applied to satisfy the demands for smaller products with increased functionality. At ever decreasing dimensions, and increasing number of input/output connections, the design of these components, in terms of dimensions and materials used, is playing a key role in determining the reliability of the final assembly. Multiphysics modeling techniques are being adopted to predict a range of interacting physics-based phenomena associated with the manufacturing process. For example, heat transfer, solidification, marangoni fluid flow, void movement, and thermal-stress. The modeling techniques used are based on finite volume methods that are conservative and take advantage of being able to represent the physical domain using an unstructured mesh. These techniques are also used to provide data on thermal induced fatigue which is then mapped into product lifetime predictions.

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Control of leaky-mode propagation and radiation properties in hybrid dielectric-waveguide printed-circuit technology: Experimental results

Experimental results are presented to show how a planar circuit, printed on a laterally shielded dielectric waveguide, can induce and control the radiation from a leaky-mode. By studying the leaky-mode complex propagation constant, a desired radiation pattern can be synthesized, controlling the main radiation characteristics (pointing direction, beamwidth, sidelobes level) for a given frequency, This technique leads to very flexible and original leaky-wave antenna designs. The experiments show to be in very good agreement with the leaky-mode theory.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

Implementation of a network flow lookup circuit for next-generation packet classifiers

This paper presents a lookup circuit with advanced memory techniques and algorithms that examines network packet headers at high throughput rates. Hardware solutions and test scenarios are introduced to evaluate the proposed approach. The experimental results show that the proposed lookup circuit is able to achieve at least 39 million packet header lookups per second, which facilitates the application of next-generation stateful packet classifications at beyond 20Gbps internet traffic throughput rates.

Design and analysis of matching circuit architectures for a closest match lookup

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. © 2006 IEEE.