Tailoring carbon nanostructure for high frequency supercapacitor operation

The possibility of enhancing the frequency performance of electrochemical capacitors by tailoring the nanostructure of the carbon electrode to increase electrolyte permeability is demonstrated. Highly porous, vertically oriented carbon electrodes which are in direct electrical contact with the metallic current collector are produced via MPECVD growth on metal foils. The resulting structure has a capacitance and frequency performance between that of an electrolytic capacitor and an electrochemical capacitor. Fully packaged devices are produced on Ni and Cu current collectors and performance compared to state-of-the-art electrochemical capacitors and electrolytic capacitors. The extension of capacitive behavior to the AC regime (100 Hz) opens up an avenue for a number of new applications where physical volume of the capacitor may be significantly reduced. © 2014 Pritesh Hiralal et al.

Enhanced charge storage characteristics of silicon nanocrystals fabricated by electron-beam coevaporation of Si and SiOx(x=1 or 2)

In this article, a simple and flexible electron-beam coevaporation (EBCE) technique has been reported of fabrication of the silicon nanocrystals (Si NCs) and their application to the nonvolatile memory. For EBCE, the Si and SiOx(x=1 or 2) were used as source materials. Transmission electron microscopy images and Raman spectra measurement verified the formation of the Si NCs. The average size and area density of the Si NCs can be adjusted by increasing the Si:O weight ratio in source material, which has a great impact on the crystalline volume fraction of the deposited film and on the charge storage characteristics of the Si NCs. A memory window as large as 6.6 V under +/- 8 V sweep voltage was observed for the metal-oxide-semiconductor capacitor structure with the embedded Si NCs.

Silicon-on-insulating multi-layers for total-dose irradiation hardness

Silicon-on-insulating multi-layer (SOIM) materials were fabricated by co-implantation of oxygen and nitrogen ions with different energies and doses. The multilayer microstructure was investigated by cross-sectional transmission electron microscopy. P-channel metal-oxide-semiconductor (PMOS) transistors and metal-semiconductor-insulator-semiconductor (MSIS) capacitors were produced by these materials. After the irradiated total dose reaches 3 x 10(5) rad (Si), the threshold voltage of the SOIM-based PMOS transistor only shifts 0.07 V, while thin silicon-on-insulating buried-oxide SIMOX-based PMOS transistors have a shift of 1.2V, where SIMOX represents the separated by implanted oxygen. The difference of capacitance of the SOIM-based MSIS capacitors before and after irradiation is less than that of the thin-box SIMOX-based MSIS capacitor. The results suggest that the SOIM materials have a more remarkable irradiation tolerance of total dose effect, compared to the thin-buried-oxide SIMOX materials.

Heteroepitaxial growth and annealing of gamma-Al2O3 thin films on silicon

The gamma-Al2O3 films were grown on Si (100) substrates using the sources of TMA (Al (CH3)(3)) and O-2 by very low-pressure chemical vapor deposition (VLP-CVD). It has been found that the gamma-Al2O3 film has a mirror-like surface and the RMS was about 2.5nm. And the orientation relationship was gamma-Al2O3(100)/Si(100). The thickness uniformity of gamma-Al2O3 films for 2-inch epi-wafer was less than 5%. The X-ray diffraction (XRD) and reflection high-energy electron diffraction (RHEED) results show that the crystalline quality of the film was improved after the film was annealed at 1000degreesC in O-2 atmosphere. The high-frequency C-V and leakage current of Al/gamma-Al2O3/Si capacitor were also measured to verify the annealing effect of the film. The results show that the dielectric constant increased from 4 to 7 and the breakdown voltage for 65-nm-thick gamma-Al2O3 film on silicon increases from 17V to 53V.

Studies of 6H-SiC devices

Silicon carbide (SiC) is recently receiving increased attention due to its unique electrical and thermal properties. It has been regarded as the most appropriate semiconductor material for high power, high frequency, high temperature, and radiation hard microelectronic devices. The fabrication processes and characterization of basic device on 6H-SiC were systematically studied. The main works are summarized as follows:The homoepitaxial growth on the commercially available single-crystal 6H-SiC wafers was performed in a modified gas source molecular beam epitaxy system. The mesa structured p(+)n junction diodes on the material were fabricated and characterized. The diodes showed a high breakdown voltage of 800 V at room temperature. They operated with good rectification characteristics from room temperature to 673 K.Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes were fabricated. They showed good rectification characteristics from room temperature to 473 K. Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800 V.n-Type 6H-SiC MOS capacitors were fabricated and characterized. Under the same growing conditions, the quality of polysilicon gate capacitors was better than Al. In addition, SiC MOS capacitors had good tolerance to gamma rays. (C) 2002 Published by Elsevier Science B.V.

Monolithic optical gates based on integration of evanescently-coupled uni-traveling-carrier photodiodes and electroabsorption modulators

We report on chip-scale optical gates based on the integration of evanescent waveguide unitraveling-carrier photodiodes (EC-UTC-PDs) and intra-step quantum well electroabsorption modulators (IQW-EAMs) on n-InP substrates. These devices exhibit simultaneously 2.1 GHz and -16.2 dB RF-gain at 21 GHz with a 450 Omega thin-film resistor and a bypass capacitor integrated on a chip.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

Heteroepitaxial growth and annealing of gamma-Al2O3 thin films on silicon

The gamma-Al2O3 films were grown on Si (100) substrates using the sources of TMA (Al (CH3)(3)) and O-2 by very low-pressure chemical vapor deposition (VLP-CVD). It has been found that the gamma-Al2O3 film has a mirror-like surface and the RMS was about 2.5nm. And the orientation relationship was gamma-Al2O3(100)/Si(100). The thickness uniformity of gamma-Al2O3 films for 2-inch epi-wafer was less than 5%. The X-ray diffraction (XRD) and reflection high-energy electron diffraction (RHEED) results show that the crystalline quality of the film was improved after the film was annealed at 1000degreesC in O-2 atmosphere. The high-frequency C-V and leakage current of Al/gamma-Al2O3/Si capacitor were also measured to verify the annealing effect of the film. The results show that the dielectric constant increased from 4 to 7 and the breakdown voltage for 65-nm-thick gamma-Al2O3 film on silicon increases from 17V to 53V.

Studies of 6H-SiC devices

Silicon carbide (SiC) is recently receiving increased attention due to its unique electrical and thermal properties. It has been regarded as the most appropriate semiconductor material for high power, high frequency, high temperature, and radiation hard microelectronic devices. The fabrication processes and characterization of basic device on 6H-SiC were systematically studied. The main works are summarized as follows:The homoepitaxial growth on the commercially available single-crystal 6H-SiC wafers was performed in a modified gas source molecular beam epitaxy system. The mesa structured p(+)n junction diodes on the material were fabricated and characterized. The diodes showed a high breakdown voltage of 800 V at room temperature. They operated with good rectification characteristics from room temperature to 673 K.Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes were fabricated. They showed good rectification characteristics from room temperature to 473 K. Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800 V.n-Type 6H-SiC MOS capacitors were fabricated and characterized. Under the same growing conditions, the quality of polysilicon gate capacitors was better than Al. In addition, SiC MOS capacitors had good tolerance to gamma rays. (C) 2002 Published by Elsevier Science B.V.

Electrochemical behaviour of TCNQ on platinum supported BLMs

The electrochemical behaviour of TCNQ modified S-BLM has been investigated through capacitor measurement and cyclic voltammetry (CV) which shows the surface wave behaviour of the TCNQ redox form. The voltammetry CV has shown different pairs peak at different scan rates and a possible explanation is provided.

Development of CMOS-compatible electrostatic supercapacitors

This work focuses on development of electrostatic supercapacitors (ESCs) using process routes compatible with complementary metal–oxide–semiconductor (CMOS) fabrication. Wafer-scale anodised aluminium oxide (AAO) processing techniques have been developed to produce high-surface area templates. Statistically optimised atomic layer deposition (ALD) processes have been developed to conformally coat the templates and generate metalinsulator-metal capacitor structures. Detailed electrical characterisation and analysis for a range of devices, revealed ESC’s with high capacitance densities of ~12 μF cm-2 and equivalent energy densities of 0.28 Wh/kg . Finally the suitability of ESC’s toward next generation energy storage applications is discussed.

Energy harvesting system design and optimization for wireless sensor networks

Wireless sensor networks (WSN) are becoming widely adopted for many applications including complicated tasks like building energy management. However, one major concern for WSN technologies is the short lifetime and high maintenance cost due to the limited battery energy. One of the solutions is to scavenge ambient energy, which is then rectified to power the WSN. The objective of this thesis was to investigate the feasibility of an ultra-low energy consumption power management system suitable for harvesting sub-mW photovoltaic and thermoelectric energy to power WSNs. To achieve this goal, energy harvesting system architectures have been analyzed. Detailed analysis of energy storage units (ESU) have led to an innovative ESU solution for the target applications. Battery-less, long-lifetime ESU and its associated power management circuitry, including fast-charge circuit, self-start circuit, output voltage regulation circuit and hybrid ESU, using a combination of super-capacitor and thin film battery, were developed to achieve continuous operation of energy harvester. Low start-up voltage DC/DC converters have been developed for 1mW level thermoelectric energy harvesting. The novel method of altering thermoelectric generator (TEG) configuration in order to match impedance has been verified in this work. Novel maximum power point tracking (MPPT) circuits, exploring the fractional open circuit voltage method, were particularly developed to suit the sub-1mW photovoltaic energy harvesting applications. The MPPT energy model has been developed and verified against both SPICE simulation and implemented prototypes. Both indoor light and thermoelectric energy harvesting methods proposed in this thesis have been implemented into prototype devices. The improved indoor light energy harvester prototype demonstrates 81% MPPT conversion efficiency with 0.5mW input power. This important improvement makes light energy harvesting from small energy sources (i.e. credit card size solar panel in 500lux indoor lighting conditions) a feasible approach. The 50mm × 54mm thermoelectric energy harvester prototype generates 0.95mW when placed on a 60oC heat source with 28% conversion efficiency. Both prototypes can be used to continuously power WSN for building energy management applications in typical office building environment. In addition to the hardware development, a comprehensive system energy model has been developed. This system energy model not only can be used to predict the available and consumed energy based on real-world ambient conditions, but also can be employed to optimize the system design and configuration. This energy model has been verified by indoor photovoltaic energy harvesting system prototypes in long-term deployed experiments.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.