Profiling of the BRCA1 transcriptome through microarray and ChIP-chip analysis

A role for BRCA1 in the direct and indirect regulation of transcription is well established. However, a comprehensive view of the degree to which BRCA1 impacts transcriptional regulation on a genome-wide level has not been defined. We performed genome-wide expression profiling and ChIP-chip analysis, comparison of which revealed that although BRCA1 depletion results in transcriptional changes in 1294 genes, only 44 of these are promoter bound by BRCA1. However, 27 of these transcripts were linked to transcriptional regulation possibly explaining the large number of indirect transcriptional changes observed by microarray analysis. We show that no specific consensus sequence exists for BRCA1 DNA binding but rather demonstrate the presence of a number of known and novel transcription factor (TF)- binding sites commonly found on BRCA1 bound promoters. Co-immunoprecipitations confirmed that BRCA1 interacts with a number of these TFs including AP2-a, PAX2 and ZF5. Finally, we show that BRCA1 is bound to a subset of promoters of genes that are not altered by BRCA1 loss, but are transcriptionally regulated in a BRCA1-dependent manner upon DNA damage. These data suggest a model, whereby BRCA1 is present on defined promoters as part of an inactive complex poised to respond to various genotoxic stimuli. © The Author(s) 2011. Published by Oxford University Press.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Image processing chip for small object detection

A new, front-end image processing chip is presented for real-time small object detection. It has been implemented using a 0.6 µ, 3.3 V CMOS technology and operates on 10-bit input data at 54 megasamples per second. It occupies an area of 12.9 mm×13.6 mm (including pads), dissipates 1.5 W, has 92 I/O pins and is to be housed in a 160-pin ceramic quarter flat-pack. It performs both one- and two-dimensional FIR filtering and a multilayer perceptron (MLP) neural network function using a reconfigurable array of 21 multiplication-accumulation cells which corresponds to a window size of 7×3. The chip can cope with images of 2047 pixels per line and can be cascaded to cope with larger window sizes. The chip performs two billion fixed point multiplications and additions per second.

Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

Investigating Hydraulically Active Fractures in A Shallow Meta-Sedimentary Bedrock Aquifer Using Single Well Tracer Testing, Mount Stewart, Northern Ireland

Knowledge of groundwater flow/mass transport, in poorly productive aquifers which underlie over 65% of the island of Ireland, is necessary for effective management of catchment water quality and aquatic ecology. This research focuses on a fractured low-grade Ordovician/Silurian greywacke sequence which underlies approximately 25% of the northern half of Ireland. Knowledge of the unit’s hydrogeological properties remain largely restricted to localised single well open hole “transmissivity” values. Current hydrogeological conceptual models of the Greywacke view the bulk of groundwater flowing through fractures in an otherwise impermeable bedrock mass.
Core analysis permits fracture characterisation, although not all identified fractures may be involved in groundwater flow. Traditional in-situ hydraulic characterisation relies on cumbersome techniques such as packer testing or geophysical borehole logging (e.g. flowmeters). Queen’s University Belfast is currently carrying out hydraulic characterization of 16 boreholes at its Greywacke Hydrogeological Research Site at Mount Stewart, Northern Ireland.
Development of dye dilution methods, using a recently-developed downhole fluorometer, provided a portable, user-friendly, and inexpensive means of detecting hydraulically active intervals in open boreholes. Measurements in a 55m deep hole, three days following fluorescent dye injection, demonstrated the ability of the technique to detect two discrete hydraulically active intervals corresponding to zones identified by caliper and heat-pulse flowmeter logs. High resolution acoustic televiewer logs revealed the zones to correspond to two steeply dipping fractured intervals. Results suggest the rock can have effective porosities of the order of 0.1%.
Study findings demonstrate dye dilution’s utility in characterizing groundwater flow in fractured aquifers. Tests on remaining holes will be completed at different times following injection to identify less permeable fractures and develop an improved understanding of the structural controls on groundwater flow in the uppermost metres of competent bedrock.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

JPEG encoder system-on-a-chip demonstrator

The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.