Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system. © 1990 Kluwer Academic Publishers.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Optimized bit level architectures for IIR filtering

Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) on every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation.

THE IMPROVED SIGN BIT ENCRYPTION OF MOTION VECTORS FOR H.264/AVC

In this paper, an improved video encryption method for encrypting the sign bit of motion vectors is proposed based on H.264/AVC, which belongs to selective encryption. This method improves upon previous work involving the sign bit encryption of motion vectors by ensuring the four candidates for the encrypted motion vectors are always located in two orthogonal lines. The improved method can provide a much more effective scrambling effect while keeping the encrypted stream format-compliant and the compression ratio unchanged. The combination of the proposed method with encryption of intra prediction modes can further enhance the scrambling effect, especially for the first few frames which are left clear when only the motion vectors are encrypted.

A Tight Upper Bound on Bit Error Rate of Joint OFDM and Multi-Carrier Index Keying

This letter investigates performance enhancement by the concept of multi-carrier index keying in orthogonal frequency division multiplexing (OFDM) systems. For the performance evaluation, a tight closed-form approximation of the bit error rate (BER) is derived introducing the expression for the number of bit errors occurring in both the index domain and the complex domain, in the presence of both imperfect and perfect detection of active multi-carrier indices. The accuracy of the derived BER results for various cases are validated using simulations, which can provide accuracy within 1 dB at favorable channels.

Bit erasure analysis of binary adders in quantum-dot cellular automata

As a post-CMOS technology, the incipient Quantum-dot Cellular Automata technology has various advantages. A key aspect which makes it highly desirable is low power dissipation. One method that is used to analyse power dissipation in QCA circuits is bit erasure analysis. This method has been applied to analyse previously proposed QCA binary adders. However, a number of improved QCA adders have been proposed more recently that have only been evaluated in terms of area and speed. As the three key performance metrics for QCA circuits are speed, area and power, in this paper, a bit erasure analysis of these adders will be presented to determine their power dissipation. The adders to be analysed are the Carry Flow Adder (CFA), Brent-Kung Adder (B-K), Ladner-Fischer Adder (L-F) and a more recently developed area-delay efficient adder. This research will allow for a more comprehensive comparison between the different QCA adder proposals. To the best of the authors' knowledge, this is the first time power dissipation analysis has been carried out on these adders.

2-bit polarisation agile antenna with high port decoupling

A practical method to achieve both decoupling and six polarisation states by employing the mode-based approach for a four-element antenna is presented. The eigenmode theory as well as a practical implementation scheme are presented. The resulting approach can operate with vertical, horizontal, slant +45°, slant -45°, right-hand circular polarisation, or left-hand circular polarisation. A prototype has been manufactured and measured results show good agreement with simulations.

A Wii Bit of Fun: A Novel Platform to Deliver Effective Balance Training to Older Adults

BACKGROUND: Falls and fall-related injuries are symptomatic of an aging population. This study aimed to design, develop, and deliver a novel method of balance training, using an interactive game-based system to promote engagement, with the inclusion of older adults at both high and low risk of experiencing a fall.

STUDY DESIGN: Eighty-two older adults (65 years of age and older) were recruited from sheltered accommodation and local activity groups. Forty volunteers were randomly selected and received 5 weeks of balance game training (5 males, 35 females; mean, 77.18 ± 6.59 years), whereas the remaining control participants recorded levels of physical activity (20 males, 22 females; mean, 76.62 ± 7.28 years). The effect of balance game training was measured on levels of functional balance and balance confidence in individuals with and without quantifiable balance impairments.

RESULTS: Balance game training had a significant effect on levels of functional balance and balance confidence (P < 0.05). This was further demonstrated in participants who were deemed at high risk of falls. The overall pattern of results suggests the training program is effective and suitable for individuals at all levels of ability and may therefore play a role in reducing the risk of falls.

CONCLUSIONS: Commercial hardware can be modified to deliver engaging methods of effective balance assessment and training for the older population.