Rapid design of biorthogonal wavelet transforms

A rapid design methodology for biorthogonal wavelet transform cores has been developed based on a generic, scaleable architecture for wavelet filters. The architecture offers efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation in a MAC-based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet system is typically less than a day. The silicon cores produced are comparable in area and performance to hand-crafted designs, The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Rapid design of discrete orthonormal wavelet transforms

A methodology which allows a non-specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilizing time-interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterized in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is designed in such a way that the cores can also be cascaded without any interface glue logic for any desired level of decomposition. This parameterization allows the use of any orthonormal wavelet family thereby extending the design space for improved transformation from algorithm to silicon. Case studies for stand alone and cascaded silicon cores for single and multi-stage analysis respectively are reported. The typical design time to produce silicon layout of a wavelet based system has been reduced by an order of magnitude. The cores are comparable in area and performance to hand-crafted designs. The designs have been captured in VHDL so they are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Rapid silicon design of discrete orthonormal wavelet transforms based algorithms

A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.

Rapid VLSI design of biorthogonal wavelet transform cores

A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterized in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Synthesizable high performance adaptive equaliser and viterbi decoder for the class-IV PRML channel

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

Rapid design of discrete orthonormal wavelet transforms using silicon IP components

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Quantization effects in the polyphase N-path IIR structure

Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL.

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.

Design of a Multiband Full-Rate Ultra-Wideband Receiver in FPGA

MultiBand OFDM (MB-OFDM) UWB [1] is a short-range promising wireless technology for high data rate communications up to 480 Mbps. In this paper, we have designed and implemented in an Virtex-6 FPGA an MB-OFDM UWB receiver for the highest data rate of 480 Mbps. To test the system, we have also implemented an MB-OFDM transmitter and an AWGN generator in VHDL and determined the bit error rates at the receiver running in an FPGA.

Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Implementation of Multi-Core Processor Based on PLASMA (Most MIPS I) IP Core

Multi-core processors is a design philosophy that has become mainstream in scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices has permitted complex logic systems to be implemented on a single programmable device. By using VHDL here we present an implementation of one multi-core processor by using the PLASMA IP core based on the (most) MIPS I ISA and give an overview of the processor architecture and share theexecution results.

Recueil de traités entre la France et l'Angleterre ; histoire d'Edouard IV et de Richard III, par Thomas Morus.

Contient : 1 Ordonnance faite par CHARLES [V], « aisné filz du roy de France et son lieutenant », en conformité des conseils donnés par l'assemblée des trois états du royaume, pour la suppression de divers abus et l'établissement de plusieurs réglements. Paris, mars 1356 ; 2 Traité de Brétigny, entre le roi de France et le roi d'Angleterre. 8 mai 1460 ; 3 Traité entre François Ier et Henri VIII, roi d'Angleterre, renouvelant et confirmant ceux qui avaient été conclus entre ledit Henri et Louis XII. Londres, 5 avril 1514 ; 4 Traité pour le mariage de Louis XII avec Marie d'Angleterre, conclu à Londres, le 14 septembre 1514 ; 5 Traité conclu entre les ambassadeurs de François Ier et ceux d'Henri VIII, roi d'Angleterre, au sujet du mariage de la princesse Marie d'Angleterre avec le dauphin. Londres, 4 octobre 1518 ; 6 Traité conclu par les mêmes pour la reddition par Henri VIII à François Ier des villes de Tournay, Saint-Amand, Mortagne, etc. Londres, 4 octobre 1518 ; 7 Traité de paix et d'alliance conclu entre la France et l'Angleterre. Londres, 2 octobre 1518 ; 8 Ratification par la régente LOUISE DE SAVOIE, du traité conclu, le 30 août précédent, par ses ambassadeurs auprès d'Henri VIII, roi d'Angleterre, qui se sont engagés à payer une somme de 2 millions de couronnes d'or. Lyon, 26 septembre 1525 ; 9 Ratification par LOUISE DE SAVOIE d'un autre traité conclu par ses ambassadeurs auprès d'Henri VIII, le 30 août précédent, pour la répression des pirateries et des pillages et la réparation des dommages subis par les sujets anglais et français. Lyon, 26 septembre 1525 ; 10 Traité conclu entre François Ier, roi de France, et Henri VIII, roi d'Angleterre. « Campaigne, ez confins d'Ardres et Guynez ». 7 juin 1546 ; 11 Traité conclu en exécution du traité précédent, pour la détermination des limites des comtés de Boulogne et de Guines. Londres, 11 mars 1547 (n. s.) ; 12 Renouvellement avec Edouard VI du traité de paix et alliance conclu par François Ier avec Henri VIII, le 7 juin 1546. Londres, 11 mars 1547 (n. s.) ; 13 « Sommaire instruction pour le faict d'Angleterre. Il est deu au roy d'Angleterre, à cause du traicté de l'an VC. XXV... » ; 14 Varia ; Notes sur les traités de 1518 et 1532, par lesquels « est faicte ligue deffensive entre le roy « de France » et le roy d'Angleterre » ; « Estat abbregé du faict d'Angleterre. Et premièrement pour les deux millions de coronnes. Par le traicté de la paix... faicte à More, en aoust mil cinq cens vingtcinq... » ; Commission donnée par FRANÇOIS Ier au cardinal Du Bellay, à Pierre Remon, seigneur de Courcelles, et à Claude de Laubespine, pour traiter de la paix avec les ambassadeurs du roi d'Angleterre. « Courtignon », 30 août 1544 ; 15 Historia Eduardi IV et Richardi III, regum Angliae, « Thoma Moro authore ». Premiers mots : « Eduardus rex, ejus nominis quartus, actis vite annis quinquaginta tribus, mensibus septem, diebus sex... » ; derniers mots : « ... Qui nepoti ejus coronando fuerat destinatus »

Design et implémentation sur FPGA d'un algorithme DES

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Implementação de um sistema de síntese de alto nível baseado em modelos java

Este trabalho apresenta uma metodologia para a geração automática de ASICs, em VHDL, a partir da linguagem de entrada Java. Como linguagem de especificação adotou-se a Linguagem Java por esta possuir características desejáveis para especificação a nível de sistema, como: orientação a objetos, portabilidade e segurança. O sistema é especificamente projetado para suportar síntese de ASICs a partir dos modelos de computação Máquina de Estados Finita e Pipeline. Neste trabalho, adotou-se estes modelos de computação por serem mais usados em sistemas embarcados As principais características exploradas são a disponibilização da geração de ASICs para a ferramenta SASHIMI, o alto nível de abstração com que o projetista pode contar em seu projeto, as otimizações de escalonamento realizadas automaticamente, e o sistema ser capaz de abstrair diferentes modelos de computação para uma descrição em VHDL. Portanto, o ambiente permite a redução do tempo de projeto e, consequentemente, dos custos agregados, diminuindo a probabilidade de erros na elaboração do projeto, portabilidade e reuso de código – através da orientação a objetos de Java – podendo-se proteger os investimentos prévios em desenvolvimento de software. A validação desses conceitos foi realizada mediante estudos de casos, utilizando-se algumas aplicações e analisando os resultados obtidos com a geração dos ASICs.