Inline Interdigital Pseudo-Elliptic Helical Resonator Filters

A new inline coupling topology for narrowband helical resonator filters is proposed that allows to introduce selectively located transmission zeros (TZs) in the stopband. We show that a pair of helical resonators arranged in an interdigital configuration can realize a large range of in-band coupling coefficient values and also selectively position a TZ in the stopband. The proposed technique dispenses the need for auxiliary elements, so that the size, complexity, power handling and insertion loss of the filter are not compromised. A second order prototype filter with dimensions of the order of 0.05 lambda, power handling capability up to 90 W, measured insertion loss of 0.18 dB and improved selectivity is presented.

Tracking Human Position and Lower Body Parts Using Kalman and Particle Filters Constrained by Human Biomechanics

In this paper, a novel framework for visual tracking of human body parts is introduced. The approach presented demonstrates the feasibility of recovering human poses with data from a single uncalibrated camera by using a limb-tracking system based on a 2-D articulated model and a double-tracking strategy. Its key contribution is that the 2-D model is only constrained by biomechanical knowledge about human bipedal motion, instead of relying on constraints that are linked to a specific activity or camera view. These characteristics make our approach suitable for real visual surveillance applications. Experiments on a set of indoor and outdoor sequences demonstrate the effectiveness of our method on tracking human lower body parts. Moreover, a detail comparison with current tracking methods is presented.

Systolic array architectures for parameterised multiplexed IIR filters

Whilst conventional bit level pipelining introduces an m cycle delay, it does allow m separate computations to be processed at throughput rates comparable to that using word level systolic arrays. We concentrate on exploiting this delay and describe a systematic method for the design of high performance multiplexed IIR filters. Two multiply and accumulate structures are identified based on shift-and-add and carry-save data organisations which can be used as building blocks in the design of IIR filters. By replacing the word level multiply and accumulate units in word level systolic structures with their equivalent bit level circuits and introducing latches to ensure correct timing, numerous architectures can be designed that process multiplexed data directly without any additional circuit overhead.

SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

Systematic methodology for the design of high performance recursive digital filters

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipe-lining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.

3D Analysis of Seepage under Hydraulic Structures with Intermediate Filters

Seepage flow under hydraulic structures provided with intermediate filters has been investigated. The flow through the banks of the canal has been included in the model. Different combinations of intermediate filter and canal width were studied. Different lengths of the floor, differential heads, and depths of the sheet pile driven beneath the floor were also investigated. The introduction of an intermediate filter to the floor of hydraulic structures reduced the uplift force acting on the downstream floor by up to 72%. The maximum uplift reduction occurred when the ratio of the distance of filter location downstream from the cutoff to the differential head was 1. Introducing a second filter in the downstream side resulted in a further reduction in the exit hydraulic gradient and in the uplift force, which reached 90%. The optimum locations of the two filters occurred when the first filter was placed just downstream of the cutoff wall and the second filter was placed nearly at the middistance between the cutoff and the end toe of the floor. The results showed significant differences between the three-dimensional (3D) and the two-dimensional (2D) analyses.

Holistic Design Strategy for High-Selectivity Low-Loss Integrated Millimetre-Wave Image-Reject Filters

To alleviate practical limitations in the design of mm-wave on-chip image-reject filters, systematic design methodologies are presented. Three low-order filters with high-selectivity and low-loss characteristics are designed and compared. Transmission zeroes are created by means of a quarter-wave transmission line (filter 1) and a series LC resonator (filters 2 and 3). Implemented on SiGe, the filters occupy 0.125, 0.064, and 0.079 mm2 chip area including pads. The measured transmission
losses across 81-86 GHz E-Band frequency range are 3.6-5.2 dB for filter 1, 3.1-4.7 dB for filter 2 and 3.6-5 dB for filter 3 where rejection levels at the image band are greater than 30 dB.