Small volume laboratory on a chip measurements incorporating the quartz crystal microbalance to measure the viscosity-density product of room temperature ionic liquids

A microfluidic glass chip system incorporating a quartz crystal microbalance (QCM) to measure the square root of the viscosity-density product of room temperature ionic liquids (RTILs) is presented. The QCM covers a central recess on a glass chip, with a seal formed by tightly clamping from above outside the sensing region. The change in resonant frequency of the QCM allows for the determination of the square root viscosity-density product of RTILs to a limit of similar to 10 kg m(-2) s(-0.5). This method has reduced the sample size needed for characterization from 1.5 ml to only 30 mu l and allows the measurement to be made in an enclosed system.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Profiling of the BRCA1 transcriptome through microarray and ChIP-chip analysis

A role for BRCA1 in the direct and indirect regulation of transcription is well established. However, a comprehensive view of the degree to which BRCA1 impacts transcriptional regulation on a genome-wide level has not been defined. We performed genome-wide expression profiling and ChIP-chip analysis, comparison of which revealed that although BRCA1 depletion results in transcriptional changes in 1294 genes, only 44 of these are promoter bound by BRCA1. However, 27 of these transcripts were linked to transcriptional regulation possibly explaining the large number of indirect transcriptional changes observed by microarray analysis. We show that no specific consensus sequence exists for BRCA1 DNA binding but rather demonstrate the presence of a number of known and novel transcription factor (TF)- binding sites commonly found on BRCA1 bound promoters. Co-immunoprecipitations confirmed that BRCA1 interacts with a number of these TFs including AP2-a, PAX2 and ZF5. Finally, we show that BRCA1 is bound to a subset of promoters of genes that are not altered by BRCA1 loss, but are transcriptionally regulated in a BRCA1-dependent manner upon DNA damage. These data suggest a model, whereby BRCA1 is present on defined promoters as part of an inactive complex poised to respond to various genotoxic stimuli. © The Author(s) 2011. Published by Oxford University Press.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Image processing chip for small object detection

A new, front-end image processing chip is presented for real-time small object detection. It has been implemented using a 0.6 µ, 3.3 V CMOS technology and operates on 10-bit input data at 54 megasamples per second. It occupies an area of 12.9 mm×13.6 mm (including pads), dissipates 1.5 W, has 92 I/O pins and is to be housed in a 160-pin ceramic quarter flat-pack. It performs both one- and two-dimensional FIR filtering and a multilayer perceptron (MLP) neural network function using a reconfigurable array of 21 multiplication-accumulation cells which corresponds to a window size of 7×3. The chip can cope with images of 2047 pixels per line and can be cascaded to cope with larger window sizes. The chip performs two billion fixed point multiplications and additions per second.

Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.