Effect of a linear potential variation on the gate of an FET

This correspondence aims at reporting the results of an analysis carried out to find the effect of a linear potential variation on the gate of an FET.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

Single‐gate deep level transient spectroscopy technique

A new deep level transient spectroscopy technique is suggested which allows the deep level parameters to be obtained from a single temperature scan. Using large ratio t2/t1 of the measurement gate positions t1 and t2 and analyzing the steep high‐temperature side of the peak, it is demonstrated that the deep level activation energy can be determined with high accuracy.

Making Sense of Value and Value Co-Creation in Service Logic

In order to further develop the logic of service, value creation, value co-creation and value have to be formally and rigorously defined, so that the nature, content and locus of value and the roles of service providers and customers in value creation can be unambiguously assessed. In the present article, following the underpinning logic of value-in-use, it is demonstrated that in order to achieve this, value creation is best defined as the customer’s creation of value-in-use. The analysis shows that the firm’s and customer’s processes and activities can be divided into a provider sphere, closed for the customer, and a customer sphere, closed for the firm. Value creation occurs in the customer sphere, whereas firms in the provider sphere facilitate value creation by producing resources and processes which represent potential value or expected value-in use for their customers. By getting access to the closed customer sphere, firms can create a joint value sphere and engage in customers’ value creation as co-creators of value with them. This approach establishes a theoretically sound foundation for understanding value creation in service logic, and enables meaningful managerial implications, for example as to what is required for co-creation of value, and also further theoretical elaborations.

A new Fuzzy-LOGIC based Model for Chlorophyll-a in Pulicat Lagoon, India

Coastal lagoons are complex ecosystems exhibiting a high degree of non-linearity in the distribution and exchange of nutrients dissolved in the water column due to their spatio-temporal characteristics. This factor has a direct influence on the concentrations of chlorophyll-a, an indicator of the primary productivity in the water bodies as lakes and lagoons. Moreover the seasonal variability in the characteristics of large-scale basins further contributes to the uncertainties in the data on the physico-chemical and biological characteristics of the lagoons. Considering the above, modelling the distributions of the nutrients with respect to the chlorophyll-concentrations, hence requires an effective approach which will appropriately account for the non-linearity of the ecosystem as well as the uncertainties in the available data. In the present investigation, fuzzy logic was used to develop a new model of the primary production for Pulicat lagoon, Southeast coast of India. Multiple regression analysis revealed that the concentrations of chlorophyll-a in the lagoon was highly influenced by the dissolved concentrations of nitrate, nitrites and phosphorous to different extents over different seasons and years. A high degree of agreement was obtained between the actual field values and those predicted by the new fuzzy model (d = 0.881 to 0.788) for the years 2005 and 2006, illustrating the efficiency of the model in predicting the values of chlorophyll-a in the lagoon.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Evidence of gate-tunable topological excitations in two-dimensional electron systems

We report experimental observations of a new mechanism of charge transport in two-dimensional electron systems (2DESs) in the presence of strong Coulomb interaction and disorder. We show that at low enough temperature the conductivity tends to zero at a nonzero carrier density, which represents the point of essential singularity in a Berezinskii-Kosterlitz-Thouless-like transition. Our experiments with many 2DESs in GaAs/AlGaAs heterostructures suggest that the charge transport at low carrier densities is due to the melting of an underlying ordered ground state through proliferation of topological defects. Independent measurement of low-frequency conductivity noise supports this scenario.

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

A survey of indian logic from the point of view of computer science

Indian logic has a long history. It somewhat covers the domains of two of the six schools (darsanas) of Indian philosophy, namely, Nyaya and Vaisesika. The generally accepted definition of Indian logic over the ages is the science which ascertains valid knowledge either by means of six senses or by means of the five members of the syllogism. In other words, perception and inference constitute the subject matter of logic. The science of logic evolved in India through three ages: the ancient, the medieval and the modern, spanning almost thirty centuries. Advances in Computer Science, in particular, in Artificial Intelligence have got researchers in these areas interested in the basic problems of language, logic and cognition in the past three decades. In the 1980s, Artificial Intelligence has evolved into knowledge-based and intelligent system design, and the knowledge base and inference engine have become standard subsystems of an intelligent system. One of the important issues in the design of such systems is knowledge acquisition from humans who are experts in a branch of learning (such as medicine or law) and transferring that knowledge to a computing system. The second important issue in such systems is the validation of the knowledge base of the system i.e. ensuring that the knowledge is complete and consistent. It is in this context that comparative study of Indian logic with recent theories of logic, language and knowledge engineering will help the computer scientist understand the deeper implications of the terms and concepts he is currently using and attempting to develop.

Automatic verification of distributed logic specifications

Formal specification is vital to the development of distributed real-time systems as these systems are inherently complex and safety-critical. It is widely acknowledged that formal specification and automatic analysis of specifications can significantly increase system reliability. Although a number of specification techniques for real-time systems have been reported in the literature, most of these formalisms do not adequately address to the constraints that the aspects of 'distribution' and 'real-time' impose on specifications. Further, an automatic verification tool is necessary to reduce human errors in the reasoning process. In this regard, this paper is an attempt towards the development of a novel executable specification language for distributed real-time systems. First, we give a precise characterization of the syntax and semantics of DL. Subsequently, we discuss the problems of model checking, automatic verification of satisfiability of DL specifications, and testing conformance of event traces with DL specifications. Effective solutions to these problems are presented as extensions to the classical first-order tableau algorithm. The use of the proposed framework is illustrated by specifying a sample problem.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

Combinatorial logic synthesis using technology directed decomposition

The aim of logic synthesis is to produce circuits which satisfy the given boolean function while meeting timing constraints and requiring the minimum silicon area. Logic synthesis involves two steps namely logic decomposition and technology mapping. Existing methods treat the two as separate operation. The traditional approach is to minimize the number of literals without considering the target technology during the decomposition phase. The decomposed expressions are then mapped on to the target technology to optimize the area, Timing optimization is carried out subsequently, A new approach which treats logic decomposition and technology maping as a single operation is presented. The logic decomposition is based on the parameters of the target technology. The area and timing optimization is carried out during logic decomposition phase itself. Results using MCNC circuits are presented to show that this method produces circuits which are 38% faster while requiring 14% increase in area.

Conflict-Tolerant Real-Time Specifications in Metric Temporal Logic

A framework based on the notion of "conflict-tolerance" was proposed in as a compositional methodology for developing and reasoning about systems that comprise multiple independent controllers. A central notion in this framework is that of a "conflict-tolerant" specification for a controller. In this work we propose a way of defining conflict-tolerant real-time specifications in Metric Interval Temporal Logic (MITL). We call our logic CT-MITL for Conflict-Tolerant MITL. We then give a clock optimal "delay-then-extend" construction for building a timed transition system for monitoring past-MITL formulas. We show how this monitoring transition system can be used to solve the associated verification and synthesis problems for CT-MITL.