Design of MIMO testbed with an FPGA board for fast signal processing

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

Implementation of a triple modular redundant FPGA based safety critical system for reliable software execution

This paper describes the implementation of a TMR (Triple Modular Redundant) microprocessor system on a FPGA. The system exhibits true redundancy in that three instances of the same processor system (both software and hardware) are executed in parallel. The described system uses software to control external peripherals and a voter is used to output correct results. An error indication is asserted whenever two of the three outputs match or all three outputs disagree. The software has been implemented to conform to a particular safety critical coding guideline/standard which is popular in industry. The system was verified by injecting various faults into it.

ASIC microcontroller design of a radiation monitoring system using VHDL modeling and FPGA implementation

Three new technologies have been brought together to develop a miniaturized radiation monitoring system. The research involved (1) Investigation a new HgI$\sb2$ detector. (2) VHDL modeling. (3) FPGA implementation. (4) In-circuit Verification. The packages used included an EG&G's crystal(HgI$\sb2$) manufactured at zero gravity, the Viewlogic's VHDL and Synthesis, Xilinx's technology library, its FPGA implementation tool, and a high density device (XC4003A). The results show: (1) Reduced cycle-time between Design and Hardware implementation; (2) Unlimited Re-design and implementation using the static RAM technology; (3) Customer based design, verification, and system construction; (4) Well suited for intelligent systems. These advantages excelled conventional chip design technologies and methods in easiness, short cycle time, and price in medium sized VLSI applications. It is also expected that the density of these devices will improve radically in the near future. ^

Logical simulation of communication subsystem for Universal Serial Bus (USB)

The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them. In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.

Implementação em FPGA de módulo de efeito de reverberação

Reverberation is caused by the reflection of the sound in adjacent surfaces close to the sound source during its propagation to the listener. The impulsive response of an environment represents its reverberation characteristics. Being dependent on the environment, reverberation takes to the listener characteristics of the space where the sound is originated and its absence does not commonly sounds like “natural”. When recording sounds, it is not always possible to have the desirable characteristics of reverberation of an environment, therefore methods for artificial reverberation have been developed, always seeking a more efficient implementations and more faithful to the real environments. This work presents an implementation in FPGAs (Field Programmable Gate Arrays ) of a classic digital reverberation audio structure, based on a proposal of Manfred Schroeder, using sets of all-pass and comb filters. The developed system exploits the use of reconfigurable hardware as a platform development and implementation of digital audio effects, focusing on the modularity and reuse characteristics

Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Implementación sobre FPGA de un algoritmo de compresión de imágenes hiperespectrales bajo el estándar CCSDS 123.0-B-1

A lo largo de la historia, nuestro planeta ha atravesado numerosas y diferentes etapas. Sin embargo, desde finales del cretácico no se vivía un cambio tan rápido como el actual. Y a la cabeza del cambio, nosotros, el ser humano. De igual manera que somos la causa, debemos ser también la solución, y el análisis a gran escala de la tierra está siendo un punto de interés para la comunidad científica en los últimos años. Prueba de ello es que, cada vez con más frecuencia, se lanzan gran cantidad de satélites cuya finalidad es el análisis, mediante fotografías, de la superficie terrestre. Una de las técnicas más versátiles para este análisis es la toma de imágenes hiperespectrales, donde no solo se captura el espectro visible, sino numerosas longitudes de onda. Suponen, eso sí un reto tecnológico, pues los sensores consumen más energía y las imágenes más memoria, ambos recursos escasos en el espacio. Dado que el análisis se hace en tierra firme, es importante una transmisión de datos eficaz y rápida. Por ello creemos que la compresión en tiempo real mediante FPGAs es la solución idónea, combinando un bajo consumo con una alta tasa de compresión, posibilitando el análisis ininterrumpido del astro en el que vivimos. En este trabajo de fin de grado se ha realizado una implementación sobre FPGA, utilizando VHDL, del estándar CCSDS 123. Este está diseñado para la compresión sin pérdida de imágenes hiperespectrales, y permite una amplia gama de configuraciones para adaptarse de manera óptima a cualquier tipo de imagen. Se ha comprobado exitosamente la validez de la implementación comparando los resultados obtenidos con otras implementaciones (software) existentes. Las principales ventajas que presentamos aquí es que se posibilita la compresión en tiempo real, obteniendo además un rendimiento energético muy prometedor. Estos resultados mejoran notablemente los de una implementación software del algoritmo, y permitirán la compresión de las imágenes a bordo de los satélites que las toman.

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but de- mand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple ap- proaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estima- tion, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, op- timizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.

Assemblage d’ADN avec graphes de de Bruijn sur FPGA

Ce mémoire est consacré à la parallélisation d’un algorithme d’assemblage d’ADN de type de novo sur différentes plateformes matérielles, soit les processeurs multicoeurs et les accélérateurs de type FPGA. Plus précisément, le langage OpenCL est utilisé pour accélérer l’algorithme dont il est question, et de permettre un comparatif direct entre les les plateformes. Cet algorithme est d’abord introduit, puis son implémentation originale, développée pour une exécution sur une grappe de noeuds, est discutée. Les modifications apportées à l’algorithme dans le but de faciliter la parallélisation sont ensuite divulgées. Ensuite, le coeur du travail est présenté, soit la programmation utilisant OpenCL. Finalement, les résultats sont présentés et discutés.

Valutazione sperimentale di algoritmi di visione stereo finalizzata a una successiva implementazione su FPGA

Applicazione di algoritmi di stereo visione con differenti configurazioni con lo scopo di confrontare e valutare quale applicare ad una successiva implementazione su FPGA.