A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

Interface adaptor logic: A new model for interfacing peripherals in IP based designs

The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.

Left-right information flow in the brain during EEG arousals

In disorders such as sleep apnea, sleep is fragmented with frequent EEG-arousal (EEGA) as determined via changes in the sleep-electroencephalogram. EEGA is a poorly understood, complicated phenomenon which is critically important in studying the mysteries of sleep. In this paper we study the information flow between the left and right hemispheres of the brain during the EEGA as manifested through inter-hemispheric asynchrony (IHA) of the surface EEG. EEG data (using electrodes A1/C4 and A2/C3 of international 10-20 system) was collected from 5 subjects undergoing routine polysomnography (PSG). Spectral correlation coefficient (R) was computed between EEG data from two hemispheres for delta-delta(0.5-4 Hz), theta-thetas(4.1-8 Hz), alpha-alpha(8.1-12 Hz) & beta-beta(12.1-25 Hz) frequency bands, during EEGA events. EEGA were graded in 3 levels as (i) micro arousals (3-6 s), (ii) short arousals (6.1-10 s), & (iii) long arousals (10.1-15 s). Our results revealed that in beta band, IHA increases above the baseline after the onset of EEGA and returns to the baseline after the conclusion of event. Results indicated that the duration of EEGA events has a direct influence on the onset of IHA. The latency (L) between the onset of arousals and IHA were found to be L=2plusmn0.5 s (for micro arousals), 4plusmn2.2 s (short arousals) and 6.5plusmn3.6 s (long arousals)