Controle de velocidade de um motor de indução trifásico usando técnicas de ajuste empírico para bancada de teste no laboratório de automação

This work aims to make the closed loop control of a three phase induction motor, through the integration of the following equipment: a frequency inverter, the actuator system; a programmable logic controller (PLC), the controller; an encoder, the velocity sensor, used as a feedback monitoring the control variable and the three-phase induction motor, the plant to be controlled. The control is performed using a Proportional - Integrative - Derivative (PID) approach. The PLC has a help instruction, which performs the auto adjustment of the controller, that instruction is used and confronted with other adjustment methods. There are several types of methods adjustments to the PID controllers, where the empirical methods are addressed in this work. The system is deployed at the Interface and Electro Electronic Control laboratory in the Universidade Estadual Paulista Júlio Mesquita Filho, Guaratinguetá, São Paulo, then, in the future, this work becomes an experiment to be conducted in the classroom, allowing undergraduate students to develop a greater affinity to the programs used by the PLC as well as studies of undergraduate and graduate works with the help of assembly made

Bit-parallel coprocessor for standard ECC-GF(2m) on FPGA

This paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC- GF(2m)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF(2163) in accordance with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein's algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs.

Reversão sexual de tilápias gift criadas em hapas e submetidas a diferentes taxas de alimentação em alta frequência

Pós-graduação em Zootecnia - FMVZ

Simulação em tempo real de sistemas de distribuição de energia elétrica utilizando-se estruturas com descrição de hardware em software

Pós-graduação em Engenharia Elétrica - FEIS

Apresentação de métodos para implementação de plataformas colaborativas de Sistemas Automatizados de Produção

Automated Production Systems Development involves aspects concerning the integration of technological components that exist on the market, such as: Programmable Logic Controllers (PLC), robot manipulators, various sensors and actuators, image processing systems, communication networks and collaborative supervisory systems; all integrated into a single application. This paper proposes an automated platform for experimentation, implemented through typical architecture for Automated Production Systems, which integrates the technological components described above, in order to allow researchers and students to carry out practical laboratory activities. These activities will complement the theoretical knowledge acquired by the students in the classroom, thus improving their training and professional skills. A platform designed using this generic structure will allow users to work within an educational environment that reflects most aspects found in Industrial Automated Manufacturing Systems, such as technology integration, communication networks, process control and production management. In addition, this platform offers the possibility complete automated process of control and supervision via remote connection through the internet (WebLab), enabling knowledge sharing between different teaching and research groups.

Análise de sistemas de proteção por redundância e bloqueio de energias contra acidentes em prensas e equipamentos rotativos

This monograph presents the main objective of analyzing the redundancy protection systems of protection for redundancy and block of energies against accident in presses and rotating equipment. After understanding two specific goals, on this case, show the systems of protection against accidents in rotating equipments, presses and similar; and discuss the vulnerabilities of current systems of protection against accidents in presses and similar, we will propose a system of autonomous redundancy of Programmable Logic Controller (PLC) operating simultaneously taking online in the event of failure of one of the two. The methodology was worked through a revision of a variety of bibliography, and interpretation of national and international standards as well as access to research on systems, practices used in industrial and companies supplying products and of companies and energy blockages solutions

Análise de sistemas de proteção por redundância e bloqueio de energias contra acidentes em prensas e equipamentos rotativos

This monograph presents the main objective of analyzing the redundancy protection systems of protection for redundancy and block of energies against accident in presses and rotating equipment. After understanding two specific goals, on this case, show the systems of protection against accidents in rotating equipments, presses and similar; and discuss the vulnerabilities of current systems of protection against accidents in presses and similar, we will propose a system of autonomous redundancy of Programmable Logic Controller (PLC) operating simultaneously taking online in the event of failure of one of the two. The methodology was worked through a revision of a variety of bibliography, and interpretation of national and international standards as well as access to research on systems, practices used in industrial and companies supplying products and of companies and energy blockages solutions

A control and automation system for wave basins

This paper presents the new active absorption wave basin, named Hydrodynamic Calibrator (HC), constructed at the University of São Paulo (USP), in the Laboratory facilities of the Numerical Offshore Tank (TPN). The square (14 m 14 m) tank is able to generate and absorb waves from 0.5 Hz to 2.0 Hz, by means of 148 active hinged flap wave makers. An independent mechanical system drives each flap by means of a 1HP servo-motor and a ball-screw based transmission system. A customized ultrasonic wave probe is installed in each flap, and is responsible for measuring wave elevation in the flap. A complex automation architecture was implemented, with three Programmable Logic Computers (PLCs), and a low-level software is responsible for all the interlocks and maintenance functions of the tank. Furthermore, all the control algorithms for the generation and absorption are implemented using higher level software (MATLAB /Simulink block diagrams). These algorithms calculate the motions of the wave makers both to generate and absorb the required wave field by taking into account the layout of the flaps and the limits of wave generation. The experimental transfer function that relates the flap amplitude to the wave elevation amplitude is used for the calculation of the motion of each flap. This paper describes the main features of the tank, followed by a detailed presentation of the whole automation system. It includes the measuring devices, signal conditioning, PLC and network architecture, real-time and synchronizing software and motor control loop. Finally, a validation of the whole automation system is presented, by means of the experimental analysis of the transfer function of the waves generated and the calculation of all the delays introduced by the automation system.

Magnetic Flip Flops for Space Applications

The radiation environment of space presents a significant threat to the reliability of nonvolatile memory technologies. Ionizing radiation disturbs the charge stored on floating gates, and cosmic rays can permanently damage thin oxides. A new memory technology based on the magnetic tunneling junction (MTJ) appears to offer superior resistance to radiation effects and virtually unlimited write endurance. A magnetic flip flop has a number of potential applications, such as the configuration memory in field-programmable logic devices. However, using MTJs in a flip flop requires radically different circuitry for storing and retrieving data. New techniques are needed to insure that magnetic flip flops are reliable in the radiation environment of space. We propose a new radiation-tolerant magnetic flip flop that uses the inherent resistance of the MTJ to increase its immunity to single event upset and employs a robust “Pac-man” magnetic element.

Design and Development of an FPGA-based Distributed Computing Processing Platform

This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using a distributed system of field-programmable gate array (FPGA) boards. The software framework providesusers with the ability to easily develop applications that exploit the processing power of FPGAs while the hardware core manager framework gives users the ability to configure and interact with multiple FPGA boards and/or hardware cores. This thesis describes the design and development of these frameworks and analyzes the performance of a system that was constructed using the frameworks. The performance analysis included measuring the effect of incorporating additional hardware components into the system and comparing the system to a software-only implementation. This work draws conclusions based on the provided results of the performance analysis and offers suggestions for future work.

Higher order parametric excitation modes for spaceborne quadrupole mass spectrometers

This paper describes a technique to significantly improve upon the mass peak shape and mass resolution of spaceborne quadrupolemass spectrometers (QMSs) through higher order auxiliary excitation of the quadrupole field. Using a novel multiresonant tank circuit, additional frequency components can be used to drive modulating voltages on the quadrupole rods in a practical manner, suitable for both improved commercial applications and spaceflight instruments. Auxiliary excitation at frequencies near twice that of the fundamental quadrupole RF frequency provides the advantages of previously studied parametric excitation techniques, but with the added benefit of increased sensed excitation amplitude dynamic range and the ability to operate voltage scan lines through the center of upper stability islands. Using a field programmable gate array, the amplitudes and frequencies of all QMS signals are digitally generated and managed, providing a robust and stable voltage control system. These techniques are experimentally verified through an interface with a commercial Pfeiffer QMG422 quadrupole rod system. When operating through the center of a stability island formed from higher order auxiliary excitation, approximately 50% and 400% improvements in 1% mass resolution and peak stability were measured, respectively, when compared with traditional QMS operation. Although tested with a circular rod system, the presented techniques have the potential to improve the performance of both circular and hyperbolic rod geometry QMS sensors.

Real Time FPGA Implementation of an Modulation Classifier for Electronic Warfare Applications

This paper presents an automatic modulation classifier for electronic warfare applications. It is a pattern recognition modulation classifier based on statistical features of the phase and instantaneous frequency. This classifier runs in a real time operation mode with sampling rates in excess of 1 Gsample/s. The hardware platform for this application is a Field Programmable Gate Array (FPGA). This AMC is subsidiary of a digital channelised receiver also implemented in the same platform.

Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly

On the automatic integration of hardware accelerators into FPGA-based embedded systems

This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration

Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.