Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

Rapid prototyping of polymeric electrophoresis microchips with integrated copper electrodes for contactless conductivity detection

A simple and easy approach to produce polymeric microchips with integrated copper electrodes for capacitively coupled contactless conductivity detection (CD) is described. Copper electrodes were fabricated using a printed circuit board (PCB) as an inexpensive thin-layer of metal. The electrode layout was first drawn and laser printed on a wax paper sheet. The toner layer deposited on the paper sheet was thermally transferred to the PCB surface working as a mask for wet chemical etching of the copper layer. After the etching step, the toner was removed with an acetonitrile-dampened cotton. A poly(ethylene terephthalate) (PET) film coated with a thin thermo-sensitive adhesive layer was used to laminate the PCB plate providing an insulator layer of the electrodes to perform CID measurements. Electrophoresis microchannels were fabricated in poly(dimethylsiloxane) (PDMS) by soft lithography and reversibly sealed against the PET film. These hybrid PDMS/PET chips exhibited a stable electroosmotic mobility of 4.25 +/- 0.04 x 10(-4) V cm(-2) s(-1), at pH 6.1, over fifty runs. Efficiencies ranging from 1127 to 1690 theoretical plates were obtained for inorganic cations.

MEMS-based incandescent microlamps for integrated optics applications

In this work we present the fabrication and operation of incandescent microlamps for integrated optics applications. This microlamp emits white and infrared light from a chromium resistor embedded in a free-standing silicon oxynitride (SiO(x)N(y)) cantilever that can be coupled to an optical waveguide. In fact, the chromium resistor is sandwiched between layers of SiO(x)N(y) that isolate it from the atmosphere, while electric current heats the resistor to incandescent temperatures. The same SiO(x)N(y) material used in the microlamp fabrication is also used to produce the optical waveguides to allow a monolithic integration of light source and optical circuit. Front-side bulk micromachining of the silicon substrate in potassium hydroxide (KOH) solution is used to fabricate the cantilevers that thermally isolate the resistors from the substrate, thus reducing the heat transfer and the current required to light the lamp.

Mechanical Testing of Indirect Composite Materials Directly Applied on Implant Abutments

Purpose: To test the strength to failure and fracture mode of three indirect composite materials directly applied onto Ti-6Al-4V implant abutments vs cemented standard porcelain-fused-to-metal (PFM) crowns. Materials and Methods: Sixty-four locking taper abutments were randomly allocated to four groups and were cleaned in ethanol in an ultrasonic bath for 5 min. After drying under ambient conditions, the abutments were grit blasted and a custom 4-cusp molar crown mold was utilized to produce identical crowns (n = 16 per group) of Tescera (Bisco), Ceramage (Shofu), and Diamond Crown (DRM) according to the manufacturer`s instructions. The porcelain-fused-to-metal crowns were fabricated by conventional means involving the construction and a wax pattern and casting of a metallic coping followed by sintering of increasing layers of porcelain. All crowns were loaded to failure by an indenter placed at one of the cusp tips at a 1 mm/min rate. Subsequently, fracture analysis was performed by means of stereomicroscopy and scanning electron microscopy. One-way ANOVA at 95% level of significance was utilized for statistical analysis. Results: The single load to failure (+/- SD) results were: Tescera (1130 +/- 239 N), Ceramage (1099 +/- 257 N), Diamond Crown (1155 +/- 284 N), and PFM (1081 +/- 243 N). Stereomicroscopy analysis showed two distinct failure modes, where the loaded cusp failed either with or without abutment/metallic coping exposure. SEM analysis of the fractures showed multiple crack propagation towards the cervical region of the crown below a region of plastic deformation at the indenter contact region. Conclusion: The three indirect composites and PFM systems fractured at loads higher than those typically associated with normal occlusal function. Although each material had a different composition and handling technique, no significant differences were found concerning their single load to fracture resistance among composite systems and PFM.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

Integrated photonic filters based on SiC multilayer structures

Combined tunable WDM converters based on SiC multilayer photonic active filters are analyzed. The operation combines the properties of active long-pass and short-pass wavelength filter sections into a capacitive active band-pass filter. The sensor element is a multilayered heterostructure produced by PE-CVD. The configuration includes two stacked SiC p-i-n structures sandwiched between two transparent contacts. Transfer function characteristics are studied both theoretically and experimentally. Results show that optical bias activated photonic device combines the demultiplexing operation with the simultaneous photodetection and self amplification of an optical signal acting the device as an integrated photonic filter in the visible range. Depending on the wavelength of the external background and irradiation side, the device acts either as a short- or a long-pass band filter or as a band-stop filter. The output waveform presents a nonlinear amplitude-dependent response to the wavelengths of the input channels. A numerical simulation and a two building-blocks active circuit are presented and give insight into the physics of the device. (c) 2013 Elsevier B.V. All rights reserved.

A 5GHz/1.8V CMOS Active Balun Integrated with LNA

The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Design and testing of a radiation hardened 13-bit 80 MS/s pipeline ADC implemented in a 90nm standard CMOS process

Second International Workshop on Analog and Mixed Signal Integrated Circuits for Space Applications (AMICSA 2008), Sintra, Portugal, Setembro de 2008

Reconfiguração e desenvolvimento do sistema de controlo de um AGV

O veículo guiado automaticamente (AGV) adquirido pelo Departamento de Engenharia Mecânica (DEM) tem vindo a ficar obsoleto devido ao hardware, que nos dias de hoje começa a dar sinais de falhas bem como falta de peças de substituição, e ao software, sendo o PLC (Programmable Logic Controller) usado muito limitado quanto às suas funções de controlo, ficando as principais tarefas de controlo do AGV a cargo de placas eletrónicas de controlo. Para promover o controlo autónomo do AGV, foi decidido retirar toda a parte de hardware que detinha o controlo do mesmo e passou a ser um novo PLC, com maior capacidade de processamento, a executar todo o tipo de controlo necessário ao funcionamento do mesmo. O hardware considerado apenas incluí, de forma resumida, os motores responsáveis pelo movimento e direção, placa de controlo de potência dos motores, placa de interface entre as saídas digitais do PLC e as entradas da placa de controlo de potência dos motores e os demais sensores necessários à deteção de obstáculos, fins de curso da direção, sensores dos postos de trabalho e avisadores de emergência. Todo o controlo de movimento e direção bem como a seleção das ações a executar passou a ficar a cargo do software programado no PLC assim como a interação entre o sistema de supervisão instalado num posto de controlo e o PLC através de comunicação via rádio. O uso do PLC permitiu a flexibilidade de mudar facilmente a forma como as saídas digitais são usadas, ao contrário de um circuito eletrónico que necessita de uma completa remodelação, tempo de testes e implementação para efetuar a mesma função. O uso de um microcontrolador seria igualmente viável para a aplicação em causa, no entanto o uso do PLC tem a vantagem de ser robusto, mais rápido na velocidade de processamento, existência de software de interface de programação bastante intuitivo e de livre acesso, facilidade de alterar a programação localmente ou remotamente, via rádio, acesso a vários protocolos de comunicação robustos como Modbus, Canbus, Profinet, Modnet, etc., e acesso integrado de uma consola gráfica totalmente programável. iv É ainda possível a sua expansão com adição de módulos de entradas e saídas digitais e/ou analógicas permitindo expandir largamente o uso do AGV para outros fins. A solução está a ser amplamente testada e validada no Laboratório de Automação (LabA) do Departamento de Engenharia Mecânica do ISEP (Instituto Superior de Engenharia do Porto), permitindo a otimização dos sistemas de controlo de direção bem como a interatividade entre o PLC e o programa de interface/supervisão do posto de trabalho.

Transimpedance amplifier for integrated SpO2 optic sensor

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

An RF LC Q-enhanced CMOS iter using integrated inductors with layout optimization

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Circuito de leitura digital para MEMS capacitivos

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores

Development of an integrated approach to reliability management and operation

The research described in this thesis has been developed as a part of the Reliability and Field Data Management for Multi-component Products (REFIDAM) Project. This project was founded under the Applied Research Grants Scheme administered by Enterprise Ireland. The project was a partnership between Galway-Mayo Institute of Technology and Thermo King Europe. The project aimed to develop a system in order to manage the information required for reliability assessment and improvement of multi-component products, by establishing information flows within the company and information exchange with fleet users.

Non-invasive RF built-in testing using on-chip temperature sensors

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.