GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Origin of flat-band voltage sharp roll-off in metal gate/high-k/ultrathin- SiO2/Si p-channel metal-oxide-semiconductor stacks

The origin of the flat band voltage roll-off (V-FB roll-off) in metal gate/high-k/ultrathin-SiO2/Si metal-oxide-semiconductor stacks is analyzed and a model describing the role of the dipoles at the SiO2/Si interface on the V-FB sharp roll-off is proposed. The V-FB sharp roll-off appears when the thickness of the SiO2 interlayer diminishes to below the oxygen diffusion depth. The results derived using our model agree well with experimental data and provide insights to the mechanism of the V-FB sharp roll-off.

Fermi-Level Pinning at Metal/High-k Interface Influenced by Electron State Density of Metal Gate

The Fermi-level pinning (FLP) at the metal/high-k interface and its dependence on the electron state density of the metal gate are investigated. It is found that the FLP is largely determined by the distortion of the vacuum level of the metal which is quantitatively ruled by the electron state density of the metal. The physical origin of the vacuum level distortion of the metal is attributed to an image charge of the interface charge in the metal. Such results indicate that the effective work function of the metal/high-k stack is also governed by the electron state density of the metal.

Poly-Si₁₋xGex Film Growth for Ni Germanosilicided Metal Gate

Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented.

Enhanced electrochemical performance of graphene nanosheet thin film anode decorated with tin nanoparticles

Graphene nanosheet (GNS) was synthesized by using microwave plasma enhanced CVD on copper substrate and followed by evaporation of tin metal. Scanning and transmission electron microscopy show that nanosize Sn particles are well embedded into the GNS matrix. The composition, structure, and electrochemical properties were characterized by X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), cyclic voltammetry (CV) and chrono-potentiometry. The first discharge capacity of as-deposited and annealed SnGNS obtained was 1551 mA h/g and 975 mA h/g, respectively. The anodes show excellent cyclic performance and coulombic efficiency.

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Microwave Plasma Assisted ALD Development for the Deposition of Gate Oxides & ALD of High-k Dielectrics

The semiconductor industry's urge towards faster, smaller and cheaper integrated circuits has lead the industry to smaller node devices. The integrated circuits that are now under volume production belong to 22 nm and 14 nm technology nodes. In 2007 the 45 nm technology came with the revolutionary high- /metal gate structure. 22 nm technology utilizes fully depleted tri-gate transistor structure. The 14 nm technology is a continuation of the 22 nm technology. Intel is using second generation tri-gate technology in 14 nm devices. After 14 nm, the semiconductor industry is expected to continue the scaling with 10 nm devices followed by 7 nm. Recently, IBM has announced successful production of 7 nm node test chips. This is the fashion how nanoelectronics industry is proceeding with its scaling trend. For the present node of technologies selective deposition and selective removal of the materials are required. Atomic layer deposition and the atomic layer etching are the respective techniques used for selective deposition and selective removal. Atomic layer deposition still remains as a futuristic manufacturing approach that deposits materials and lms in exact places. In addition to the nano/microelectronics industry, ALD is also widening its application areas and acceptance. The usage of ALD equipments in industry exhibits a diversi cation trend. With this trend, large area, batch processing, particle ALD and plasma enhanced like ALD equipments are becoming prominent in industrial applications. In this work, the development of an atomic layer deposition tool with microwave plasma capability is described, which is a ordable even for lightly funded research labs.

Studies on pyridinium hexafluorostannate and its derivatives

Pyridinium hexafluorostannate, (C5H5NH)2SnF6, has been prepared by the reaction of stannous chloride or tin metal with pyridinium poly(hydrogen fluoride), PPHF, and identified by chemical analysis, IR and NMR (H-1, F-19, C-13). Making use of (C5H5NH)2SnF6 as a precursor, the following important hexafluorostannate salts have been synthesized in high yields at room temperature by ionic exchange: M2SnF6 (M = NH4, Na, K, Rb, Cs) and BaSnF6. These salts have been characterised by chemical analysis and infrared spectroscopy. Indexed powder X-ray diffraction data for Na2SnF6, Rb2SnF6 and Cs2SnF6 have been reported.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.

Highly electron transparent Graphene for field emission triode gates

The enhanced emission performance of a graphene/Mo hybrid gate electrode integrated into a nanocarbon field emission micro-triode electron source is presented. Highly electron transparent gate electrodes are fabricated from chemical vapor deposited bilayer graphene transferred to Mo grids with experimental and simulated data, showing that liberated electrons efficiently traverse multi-layer graphene membranes with transparencies in excess of 50-68%. The graphene hybrid gates are shown to reduce the gate driving voltage by 1.1 kV, whilst increasing the electron transmission efficiency of the gate electrode significantly. Integrated intensity maps show that the electron beam angular dispersion is dramatically improved (87.9°) coupled with a 63% reduction in beam diameter. Impressive temporal stability is noted (<1.0%) with surprising negligible long-term damage to the graphene. A 34% increase in triode perveance and an amplification factor 7.6 times that of conventional refractory metal grid gate electrode-based triodes are noted, thus demonstrating the excellent stability and suitability of graphene gates in micro-triode electron sources. A nanocarbon field emission triode with a hybrid gate electrode is developed. The graphene/Mo gate shows a high electron transparency (50-68%) which results in a reduced turn-on potential, increased beam collimation, reduced beam diameter (63%), enhanced stability (<1% variation), a 34% increase in perveance, and an amplification 7.6 times that of equivalent conventional refractory metal gate triodes. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Atom probe tomography of SRAM transistors: Specimen preparation methods and analysis

Different FIB-based sample preparation methods for atom probe analysis of transistors have been proposed and discussed. A special procedure, involving device deprocessing, has been used to analyze by APT a sub-30 nm transistor extracted from a SRAM device. The analysis provides three dimensional compositions of Ni-silicide contact, metal gate and high-k oxide of the transistor gate. © 2013 Elsevier B.V. All rights reserved.

Atom probe tomography for advanced metallization

In microelectronics, the increase in complexity and the reduction of devices dimensions make essential the development of new characterization tools and methodologies. Indeed advanced characterization methods with very high spatial resolution are needed to analyze the redistribution at the nanoscale in devices and interconnections. The atom probe tomography has become an essential analysis to study materials at the nanometer scale. This instrument is the only analytical microscope capable to produce 3D maps of the distribution of the chemical species with an atomic resolution inside a material. This technique has benefit from several instrumental improvements during last years. In particular, the use of laser for the analysis of semiconductors and insulating materials offers new perspectives for characterization. The capability of APT to map out elements at the atomic scale with high sensitivity in devices meets the characterization requirements of semiconductor devices such as the determination of elemental distributions for each device region. In this paper, several examples will show how APT can be used to characterize and understand materials and process for advanced metallization. The possibilities and performances of APT (chemical analysis of all the elements, atomic resolution, planes determination, crystallographic information...) will be described as well as some of its limitations (sample preparation, complex evaporation, detection limit, ...). The examples illustrate different aspect of metallization: dopant profiling and clustering, metallic impurities segregation on dislocation, silicide formation and alloying, high K/metal gate optimization, SiGe quantum dots, as well as analysis of transistors and nanowires. © 2013 Elsevier B.V. All rights reserved.