BACKGATING AND LIGHT SENSITIVITY IN GAAS METAL-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

Three different types of GaAs metal-semiconductor field effect transistors (MESFET) by employing ion implantation, molecular beam epitaxy (MBE) and low-temperature MBE (LT MBE) techniques respectively were fabricated and studied in detail. The backgating (sidegating) measurement in the dark and in the light were carried out. For the LT MBE-GaAs buffered MESFETs, the output resistance R(d) and the peak transconductance g(m) were measured to be above 50 k Omega and 140 mS/mm, respectively, and the backgating and light sensitivity were eliminated. A theoretical model describing the light sensitivity in these kinds of devices is given. and good agreement with experimental data is reached.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3 degrees-7 degrees twist or wrap and 0.3-0.7 angstrom ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green's function approach. We study the channel density of states, transmission spectra, and the I-D-V-D characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple. (C) 2013 AIP Publishing LLC.

Performance analysis of boron nitride embedded armchair graphene nanoribbon metal-oxide-semiconductor field effect transistor with Stone Wales defects

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width similar to 5 nm, the simulated ON current is found to be in the range of 265 mu A-280 mu A with an ON/OFF ratio 7.1 x 10(6)-7.4 x 10(6) for a V-DD = 0.68 V corresponding to 10 nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%. (C) 2014 AIP Publishing LLC.

Trapped charge dynamics in a sol-gel based TiO(2) high- k gate dielectric silicon metal-oxide-semiconductor field effect transistor.

We have studied the response of a sol-gel based TiO(2), high k dielectric field effect transistor structure to microwave radiation. Under fixed bias conditions the transistor shows frequency dependent current fluctuations when exposed to continuous wave microwave radiation. Some of these fluctuations take the form of high Q resonances. The time dependent characteristics of these responses were studied by modulating the microwaves with a pulse signal. The measurements show that there is a shift in the centre frequency of these high Q resonances when the pulse time is varied. The measured lifetime of these resonances is high enough to be useful for non-classical information processing.

Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Threshold behavior in backgating in GaAs metal-semiconductor field-effect transistors: Induced by limitation of channel-substrate junction to leakage current

An analytical model is proposed to understand backgating in GaAs metal-semiconductor field-effect transistors (MESFETs), in which the effect of channel-substrate (CS) junction is included. We have found that the limitation of CS junction to leakage current will cause backgate voltage to apply directly to CS junction and result in a threshold behavior in backgating effect. A new and valuable expression for the threshold voltage has been obtained. The corresponding threshold electric field is estimated to be in the range of 1000-4000 V/cm and for the first time is in good agreement with reported experimental data. More, the eliminated backgating effect in MESFETs that are fabricated on the GaAs epitaxial layer grown at low temperature is well explained by our theory. (C) 1997 American Institute of Physics.

Multiple valley couplings in nanometer Si metal-oxide-semiconductor field-effect transistors

We investigate the couplings between different energy band valleys in a metal-oxide-semiconductor field-effect transistor (MOSFET) device using self-consistent calculations of million-atom Schrodinger-Poisson equations. Atomistic empirical pseudopotentials are used to describe the device Hamiltonian and the underlying bulk band structure. The MOSFET device is under nonequilibrium condition with a source-drain bias up to 2 V and a gate potential close to the threshold potential. We find that all the intervalley couplings are small, with the coupling constants less than 3 meV. As a result, the system eigenstates derived from different bulk valleys can be calculated separately. This will significantly reduce the simulation time because the diagonalization of the Hamiltonian matrix scales as the third power of the total number of basis functions. (C) 2008 American Institute of Physics.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

INTERFACIAL REACTIONS IN THE CO/SI/GAAS AND SI/CO/GAAS SYSTEMS

The interfacial reactions between thin films of cobalt and silicon and (100)-oriented GaAs substrates in two configurations, Co/Si/GaAs and Si/Co/GaAs, were studied using a variety of techniques including Auger electron spectroscopy, x-ray diffraction, and transmission electron microscopy. The annealing conditions were 200, 300, 400, 600-degrees-C for 30 min, and rapid thermal annealing for 15 s. It was found that Si layer in the Co/Si/GaAs system acts as a barrier at the interface between Co and GaAs when annealed up to 600-degrees-C. The interfacial reaction between Co and Si is faster than that between Co and GaAs in the system of Si/Co/GaAs. The sequence of compound formation for the two metallizations studied (Co/Si/GaAs and Si/Co/GaAs) depends strongly on the sample configuration as well as the layer thickness of Si and Co (Co/Si atomic ratio). From our results, it is promising to utilize Co/Si/GaAs multilayer film structure to make a CoSi2/GaAs contact, and this CoSi2 may offer an alternative to the commonly used W silicides as improved gate metallurgies in self-aligned metal-semiconductor field effect transistor (MESFET) technologies.

A study of the effects metal residues in poly(9,9-dioctylfluorene) have on field-effect transistor device characteristics

The amount of metal residues from organometallic reagents used in preparation of poly(9,9-dioctylfluorene) by palladium catalysed Suzuki and nickel-induced Yamamoto polycondensations have been determined, and their effect upon the behaviour of the polymer in field-effect transistors (FETs) has been measured. The metal levels from material polymerised by Suzuki method were found to be much higher than from that made by the Yamamoto procedure. Simple treatment of the polymers with suitable metal trapping reagents lowered the metal levels significantly, with EDTA giving best results for nickel and triphenylphosphine for palladium. Comparison of the behaviour of FETs using polyfluorenes with varying levels of metal contamination, showed that the metal residues have little effect upon the mobility values, but often affect the degree of hysteresis, possibly acting as charge traps. Satisfactory device performances were obtained from polymer with palladium levels of 2000 μg/g suggesting that complete removal of metal residues may not be necessary for satisfactory device performance.

Photoimpedance characterization of polymer field-effect transistor

The small signal ac response is measured across the source-drain terminals of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) field-effect transistor under dc bias to obtain the equivalent circuit parameters in the dark, and under a monochromatic light (540 nm) of various intensities. The numerically simulated response based on these parameters shows deviation at low frequency which is related to the charge accumulation at the interface and the contact resistance at the electrodes. This method can be used to differentiate the photophysical phenomena occurring in the bulk from that at the metal-semiconductor interface for polymer field-effect transistors. ©2009 American Institute of Physics