A new chemorheological analysis of highly filled thermosets used in integrated circuit packaging

Chemorheology (and thus process modeling) of highly filled thermosets used in integrated circuit (IC) packaging has been complicated by their highly filled nature, fast kinetics of curing, and viscoelastic nature. This article summarizes a more thorough chemorheological analysis of a typical IC packaging thermoset material, including novel isothermal and nonisothermal multiwave parallel-plate chemorheology. This new chemorheological analysis may be used to optimize existing and design new IC packaging processes. (C) 1997 John Wiley & Sons, Inc.

Arrays of gold microelectrodes made from split integrated circuit chips

A simple and inexpensive way to fabricate arrays of gold microelectrodes is proposed. Integrated circuit chips are sawed through their middle, normal to the longest axis, leading to destruction of the silicon circuit and rupture of the gold wires that interconnect it with the external terminals. Polishing the resulting rough surface converts the tips of the wires embedded in the chip halves into arrays of gold microdisks of about 25 mu m diameter. The number of active microelectrodes (MEs), of an array depends on the number of pins in the chip, n, being typically (n/2)-4. These MEs can be used individually or externally interconnected in any combination. X-ray images of the chips and micrographs of the resulting surface of the polished arrays have revealed variable distances between neighbor MEs, which are, however, larger than 10 times the radius of the disks. This feature of the MEs prevents diffusional cross-talk between electrodes. The use of these microdisk electrodes for analytical purposes exhibits sigmoidal voltammograms, and chronoamperometric experiments confirm the nonlinear i vs. t(1/2) plots, typical for processes where radial diffusion prevails. Satisfactory uniformity was observed for the response of each electrode of an array, indicating similarity of geometry and disk areas. The potentialities of these MEs were demonstrated by the determination of cadmium at ppb levels using square wave voltammetry with preconcentration. Due to the relative ease with which these MEs can be manufactured and their good performance in (chemical) analysis, wide applications in electrochemistry and electroanalysis is envisioned.

Flow-through cell based on an array of gold microelectrodes obtained from modified integrated circuit chips

The construction of a flow-through cell incorporating an array of gold microelectrodes is described and its application to flow injection analysis with amperometric detection is presented, Simple modification of almost any conventional integrated circuit chip, used as an inexpensive source of pre-assembled gold micro-wires, leads to the rapid and successful preparation of arrays of 8-48 elements, the polymeric encapsulation material from the top face of the chip is removed by abrasion until the gold micro-mires (used to interconnect the silicon circuit to the external contact pins of the chip) are disrupted and their transversal (elliptical) sections become exposed. Once polished, the flat and smooth top surface of the gold microelectrode-array chip (MEAC) is provided with a spacer and fitted under pressure against an acrylic block with the reference and auxiliary electrodes, to form the electrochemical (thin-layer) flow cell, while the contact pins are plugged into a standard IC socket, This design ensures autonomous electric contact with each electrode and allows fast dismantling for polishing or substitution, the performance of flow cells with MEACs was investigated utilizing the technique of reverse pulse amperometry without oxygen removal, A method was established for the determination of the copper concentration in sugar cane spirit, regulated by law for beverages, Samples from industrial producers and small-scale (alembic) brewers were compared, With a 24 MEAC, a detection limit of 30 mu g I-l of copper (4.7 x 10(-7) mol l(-1) of Cu-II for 100 mu l injections) was calculated, Routine operation was established at a frequency of 60-90 determinations per hour, Intercomparison with atomic absorption spectrometric determinations resulted in excellent agreement.

Accurate linewidth measurements on integrated-circuit photomasks /

"Supported by the Defense Advanced Research Projects Agency ... and the National Bureau of Standards."

Chemical studies of plasma etchants used in integrated circuit manufacture

Plasma or "dry" etching is an essential process for the production of modern microelectronic circuits. However, despite intensive research, many aspects of the etch process are not fully understood. The results of studies of the plasma etching of Si and Si02 in fluorine-containing discharges, and the complementary technique of plasma polymerisation are presented in this thesis. Optical emission spectroscopy with argon actinometry was used as the principle plasma diagnostic. Statistical experimental design was used to model and compare Si and Si02 etch rates in CF4 and SF6 discharges as a function of flow, pressure and power. Etch mechanisms m both systems, including the potential reduction of Si etch rates in CF4 due to fluorocarbon polymer formation, are discussed. Si etch rates in CF4 /SF6 mixtures were successfully accounted for by the models produced. Si etch rates in CF4/C2F6 and CHF3 as a function of the addition of oxygen-containing additives (02, N20 and CO2) are shown to be consistent with a simple competition between F, 0 and CFx species for Si surface sites. For the range of conditions studied, Si02 etch rates were not dependent on F-atom concentration, but the presence of fluorine was essential in order to achieve significant etch rates. The influence of a wide range of electrode materials on the etch rate of Si and Si02 in CF4 and CF4 /02 plasmas was studied. It was found that the Si etch rate in a CF4 plasma was considerably enhanced, relative to an anodised aluminium electrode, in the presence of soda glass or sodium or potassium "doped" quartz. The effect was even more pronounced in a CF4 /02 discharge. In the latter system lead and copper electrodes also enhanced the Si etch rate. These results could not be accounted for by a corresponding rise in atomic fluorine concentration. Three possible etch enhancement mechanisms are discussed. Fluorocarbon polymer deposition was studied, both because of its relevance to etch mechanisms and its intrinsic interest, as a function of fluorocarbon source gas (CF4, C2F6, C3F8 and CHF3), process time, RF power and percentage hydrogen addition. Gas phase concentrations of F, H and CF2 were measured by optical emission spectroscopy, and the resultant polymer structure determined by X-ray photoelectron spectroscopy and infrared spectroscopy. Thermal and electrical properties were measured also. Hydrogen additions are shown to have a dominant role in determining deposition rate and polymer composition. A qualitative description of the polymer growth mechanism is presented which accounts for both changes in growth rate and structure, and leads to an empirical deposition rate model.

Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design

To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the efficient solutions. At the circuit level, a new reliability-driven minimum cost Steiner routing and layer assignment scheme is proposed, and the first transceiver insertion algorithmic framework for the optical interconnect is proposed. At the system level, a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems, which optimizes system energy consumption under stochastic fault occurrences, is proposed. The embedded system design is also widely used in the smart home area for improving health, wellbeing and quality of life. The proposed scheduling scheme for multiprocessor embedded systems is hence extended to handle the energy consumption scheduling issues for smart homes. The extended scheme can arrange the household appliances for operation to minimize monetary expense of a customer based on the time-varying pricing model.

A radial basis function network (RBFN) for function approximation

A radial basis function network (RBFN) circuit for function approximation is presented. Simulation and experimental results show that the network has good approximation capabilities. The RBFN was a squared hyperbolic secant with three adjustable parameters amplitude, width and center. To test the network a sinusoidal and sine function,vas approximated.

An analog implementation of radial basis function network appropriate for transducer linearizer

A circuit for transducer linearizer tasks have been designed and built using discrete components and it implements by: a Radial Basis Function Network (RBFN) with three basis functions. The application in a linearized thermistor showed that the network has good approximation capabilities. The circuit advantages is the amplitude, width and center.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

VLSI testing and characterization system for micro electro-mechanical (MEM) sensors

The purpose of this investigation was to develop and implement a general purpose VLSI (Very Large Scale Integration) Test Module based on a FPGA (Field Programmable Gate Array) system to verify the mechanical behavior and performance of MEM sensors, with associated corrective capabilities; and to make use of the evolving System-C, a new open-source HDL (Hardware Description Language), for the design of the FPGA functional units. System-C is becoming widely accepted as a platform for modeling, simulating and implementing systems consisting of both hardware and software components. In this investigation, a Dual-Axis Accelerometer (ADXL202E) and a Temperature Sensor (TMP03) were used for the test module verification. Results of the test module measurement were analyzed for repeatability and reliability, and then compared to the sensor datasheet. Further study ideas were identified based on the study and results analysis. ASIC (Application Specific Integrated Circuit) design concepts were also being pursued.

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1)

Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e Sistemas

A physical frequency-dependent compact model for RF integrated inductors

A frequency-dependent compact model for inductors in high ohmic substrates, which is based on an energy point-of-view, is developed. This approach enables the description of the most important coupling phenomena that take place inside the device. Magnetically induced losses are quite accurately calculated and coupling between electric and magnetic fields is given by means of a delay constant. The later coupling phenomenon provides a modified procedure for the computation of the fringing capacitance value, when the self-resonance frequency of the inductor is used as a fitting parameter. The model takes into account the width of every metal strip and the pitch between strips. This enables the description of optimized layout inductors. Data from experiments and electromagnetic simulators are presented to test the accuracy of the model.

A current-mode interface circuit for a piezoresistive pressure sensor

An interfacing circuit for piezoresistive pressure sensors based on CMOS current conveyors is presented. The main advantages of the proposed interfacing circuit include the use of a single piezoresistor, the capability of offset compensation, and a versatile current-mode configuration, with current output and current or voltage input. Experimental tests confirm linear relation of output voltage versus piezoresistance variation.

Improvement of the quality factor of RF integrated inductors by layout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency.