An Error-Localization, Validation and Optimization Tool for Embedded Code Augmentation: an Architecture Oriented Approach

Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.This dissertation contributes to an architecture oriented code validation, error localization and optimization technique assisting the embedded system designer in software debugging, to make it more effective at early detection of software bugs that are otherwise hard to detect, using the static analysis of machine codes. The focus of this work is to develop methods that automatically localize faults as well as optimize the code and thus improve the debugging process as well as quality of the code.Validation is done with the help of rules of inferences formulated for the target processor. The rules govern the occurrence of illegitimate/out of place instructions and code sequences for executing the computational and integrated peripheral functions. The stipulated rules are encoded in propositional logic formulae and their compliance is tested individually in all possible execution paths of the application programs. An incorrect sequence of machine code pattern is identified using slicing techniques on the control flow graph generated from the machine code.An algorithm to assist the compiler to eliminate the redundant bank switching codes and decide on optimum data allocation to banked memory resulting in minimum number of bank switching codes in embedded system software is proposed. A relation matrix and a state transition diagram formed for the active memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Instances of code redundancy based on the stipulated rules for the target processor are identified.This validation and optimization tool can be integrated to the system development environment. It is a novel approach independent of compiler/assembler, applicable to a wide range of processors once appropriate rules are formulated. Program states are identified mainly with machine code pattern, which drastically reduces the state space creation contributing to an improved state-of-the-art model checking. Though the technique described is general, the implementation is architecture oriented, and hence the feasibility study is conducted on PIC16F87X microcontrollers. The proposed tool will be very useful in steering novices towards correct use of difficult microcontroller features in developing embedded systems.

Realization of Optical Logic Gates Using the Thermal Lens Effect

A sensitive method based on the principle of photothermal phenomena to realize optical logic gates is presented. A dual beam thermal lens method using low power cw lasers in a dye-doped polymer can be very effectively used as an alternate technique to perform the logical function such as NAND, AND and OR.

Haematology of Fenneropenaeus indicus in response to environmental alterations and microbial infections

Aquaculture has developed to become one of the fastest growing food producing sectors in the world.Today India is one among the major shrimp producing countries in the world.There are extensive and intensive shrimp culture practices. In extensive shrimp culture, shrimps are stocked at low densities (< 25 PLs m'2)in large ponds or tidal enclosures in which little or no management is exercised or possible. Farmers depend almost entirely on natural conditions in extensive cultures. Intensive shrimp culture is carried out in high densities (>200 PLs m'2). Much of the world shrimp production still comes from extensive culture.There is a growing demand for fish and marine products for human and animal consumption. This demand has led to rapid growth of aquaculture, which some times has been accompanied by ecological impacts and economic loss due to diseases. The expansion of shrimp culture always accompanies local environmental degradation and occurrence of diseases.Disease out breaks is recognised as a significant constraint to aquaculture production. Environmental factors, water quality, pollution due to effluent discharge and pathogenic invasion due to vertical and horizontal transmission are the main causes of shrimp disease out breaks. Nutritional imbalance, toxicant and other pollutants also account for the onset of diseases. pathogens include viruses, bacteria, fungi and parasites.Viruses are the most economically significant pathogens of the cultured shrimps world wide. Disease control in shrimp aquaculture should focus first on preventive measures for eliminating disease promoting factors.ln order to design prophylactic and proactive measures against shrimp diseases, it is mandatory to understand the immune make up of the cultivable species, its optimum culture conditions and the physico chemical parameters of the rearing environment. It has been proven beyond doubt that disease is an end result of complex interaction of environment, pathogen and the host animal. The aquatic environment is abounded with infectious microbes.The transmission of disease in this environment is extremely easy, especially under dense, culture conditions. Therefore, a better understanding of the immune responses of the cultured animal in relation to its environmental alterations and microbial invasions is essential indevising strategic measures against aquaculture loss due to diseases. This study accentuate the importance of proper and regular health monitoring in shrimps employing the most appropriate haematological biomarkers for application of suitable prophylactic measures in order to avoid serious health hazards in shrimp culture systems.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.

Almost Self-Centered Median And Chordal Graphs

Almost self-centered graphs were recently introduced as the graphs with exactly two non-central vertices. In this paper we characterize almost selfcentered graphs among median graphs and among chordal graphs. In the first case P4 and the graphs obtained from hypercubes by attaching to them a single leaf are the only such graphs. Among chordal graph the variety of almost self-centered graph is much richer, despite the fact that their diameter is at most 3. We also discuss almost self-centered graphs among partial cubes and among k-chordal graphs, classes of graphs that generalize median and chordal graphs, respectively. Characterizations of almost self-centered graphs among these two classes seem elusive