Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Caracterització d'oscil·ladors basats en CMOS-M/NEMS i la seva aplicació com a sensors de massa

El present projecte tracta sobre la caracterització d'oscil·ladors basats en ressonadors micro/nanoelectromecànics (M/NEMS) i la seva aplicació com a sensors de massa. Els oscil·ladors utilitzats es basen en un pont i una palanca ressoants M/NEMS, integrats en tecnologia CMOS. En primer lloc s'ha fet una introducció teòrica als conceptes utilitzats per a entendre el funcionament i la caracterització dels dispositius. A continuació s'han realitzat proves per tal de caracteritzar els paràmetres importants per a l'ús dels oscil·ladors com a sensors de massa, com la seva estabilitat en freqüència. Per acabar s'han aplicat aquests sensors en la caracterització i modelització del flux de massa a través d'obertures de dimensions micromètriques.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

A gated single-photon avalanche diode array fabricated in a conventional CMOS process for triggered systems

A bidimensional array based on single-photon avalanche diodes for triggered imaging systems is presented. The diodes are operated in the gated mode of acquisition to reduce the probability to detect noise counts interfering with photon arrival events. In addition, low reverse bias overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process gets rid of afterpulses and offers a reduced dark count probability by applying the proposed modes of operation. The detector exhibits a dynamic range of 15 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 1.0V.

Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

Readout schemes for low noise single-photon avalanche diodes fabricated in conventional HV-CMOS technologies

Three different pixels based on single-photon avalanche diodes for triggered applications, such as fluorescence lifetime measurements and high energy physics experiments, are presented. Each pixel consists of a 20µm x 100µm (width x length) single photon avalanche diode and a monolithically integrated readout circuit. The sensors are operated in the gated mode of acquisition to reduce the probability to detect noise counts interferring with real radiation events. Each pixel includes a different readout circuit that allows to use low reverse bias overvoltages. Experimental results demonstrate that the three pixels present a similar behaviour. The pixels get rid of afterpulses and present a reduced dark count probability by applying the gated operation. Noise figures are further improved by using low reverse bias overvoltages. The detectors exhibit an input dynamic range of 13.35 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 0.5V. The three pixels have been fabricated in a standard HV-CMOS process.

Readout electronics for low dark count pixel detectors based on geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

The high sensitivity and excellent timing accuracy of Geiger mode avalanche photodiodes makes them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase of the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 µm and a high integration 0.13 µm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

Low dark count geiger mode avalanche photodiodes fabricated in conventional CMOS technologies

Avalanche photodiodes operated in the Geiger mode present very high intrinsic gain and fast time response, which make the sensor an ideal option for those applications in which detectors with high sensitivity and velocity are required. Moreover, they are compatible with conventional CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. Despite these excellent qualities, the photodiode suffers from high intrinsic noise, which degrades the performance of the detector and increases the memory area to store the total amount of information generated. In this work, a new front-end circuit that allows low reverse bias overvoltage sensor operation to reduce the noise in Geiger mode avalanche photodiode pixel detectors is presented. The proposed front-end circuit also enables to operate the sensor in the gated acquisition mode to further reduce the noise. Experimental characterization of the fabricated pixel with the conventional HV-AMS 0.35µm technology is also presented in this article.

Métodos de extracción de parámetros de un circuito equivalente de pequeña señal para transistores LDMOS de potencia para aplicaciones de RF

En la actualidad, la gran cantidad de aplicaciones que surgen dentro del ámbito de la radiofrecuencia hacen que el desarrollo de dispositivos dentro de este campo sea constante. Estos dispositivos cada vez requieren mayor potencia para frecuencias de trabajo elevadas, lo que sugiere abrir vías de investigación sobre dispositivos de potencia que ofrezcan los resultados deseados para altas frecuencias de operación (GHz). Dentro de este ámbito, el objetivo principal de este proyecto es el de realizar un estudio sobre este tipo de dispositivos, siendo el transistor LDMOS el candidato elegido para tal efecto, debido a su buen comportamiento en frecuencia para tensiones elevadas de funcionamiento.

Desarrollo de tecnología Bulk Acoustic Wave

El creciente uso de dispositivos móviles y el gran avance en la mejora de las aplicaciones y sistemas inalámbricos ha impulsado la demanda de filtros paso banda miniaturizados, que trabajen a altas frecuencias y tengan unas prestaciones elevadas. Los filtros basados en resonadores Bulk Acoustic Wave (BAW) están siendo la mejor alternativa a los filtros Surface Acoustic Wave (SAW), ya que funcionan a frecuencias superiores, pueden trabajar a mayores niveles de potencia y son compatibles con la tecnología CMOS. El filtro en escalera, que utiliza resonadores BAW, es de momento la mejor opción, debido a su facilidad de diseño y su bajo coste de fabricación. Aunque el filtro con resonadores acoplados (CRF) presenta mejores prestaciones como mayor ancho de banda, menor tamaño y conversión de modos. El problema de este tipo de filtros reside en su complejidad de diseño y su elevado coste. Este trabajo lleva a cabo el diseño de un CRF a partir de unas especificaciones bastante estrictas, demostrando sus altas prestaciones a pesar de su mayor inconveniente: el coste de fabricación.

Non-invasive RF built-in testing using on-chip temperature sensors

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.

Bipolar pulsed excitation of erbium-doped nanosilicon light emitting diodes

High quantum efficiency erbium doped silicon nanocluster (Si-NC:Er) light emitting diodes (LEDs) were grown by low-pressure chemical vapor deposition (LPCVD) in a complementary metal-oxide-semiconductor (CMOS) line. Erbium (Er) excitation mechanisms under direct current (DC) and bipolar pulsed electrical injection were studied in a broad range of excitation voltages and frequencies. Under DC excitation, Fowler-Nordheim tunneling of electrons is mediated by Er-related trap states and electroluminescence originates from impact excitation of Er ions. When the bipolar pulsed electrical injection is used, the electron transport and Er excitation mechanism change. Sequential injection of electrons and holes into silicon nanoclusters takes place and nonradiative energy transfer to Er ions is observed. This mechanism occurs in a range of lower driving voltages than those observed in DC and injection frequencies higher than the Er emission rate.

Low noise pixel detectors based on gated geiger mode avalanche photodiodes

The gated operation is proposed as an effective method to reduce the noise in pixel detectors based on Geiger mode avalanche photodiodes. A prototype with the sensor and the front-end electronics monolithically integrated has been fabricated with a conventional HV-CMOS process. Experimental results demonstrate the increase of the dynamic range of the sensor by applying this technique.

Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to erroneous results and limit the range of detectable signals. They also increase the amount of data that has to be stored. In this work, we present a pixel based on a Geiger-mode avalanche photodiode operated in the gated mode to reduce the probability to detect noise counts interfering with photon arrival events. The readout circuit is based on a two grounds scheme to enable low reverse bias overvoltages and consequently lessen the dark count rate. Experimental characterization of the fabricated pixel with the HV-AMS 0.35µm standard technology is also presented in this article.