Desarrollo de software para el procesado numérico en tarjetas gráficas

Debido al gran número de transistores por mm2 que hoy en día podemos encontrar en las GPU convencionales, en los últimos años éstas se vienen utilizando para propósitos generales gracias a que ofrecen un mayor rendimiento para computación paralela. Este proyecto implementa el producto sparse matrix-vector sobre OpenCL. En los primeros capítulos hacemos una revisión de la base teórica necesaria para comprender el problema. Después veremos los fundamentos de OpenCL y del hardware sobre el que se ejecutarán las librerías desarrolladas. En el siguiente capítulo seguiremos con una descripción del código de los kernels y de su flujo de datos. Finalmente, el software es evaluado basándose en comparativas con la CPU.

Hydrogen-induced changes in the breakdown voltage of InP HEMTs

In this work, electrical measurements show that the breakdown voltage,BVDG, of InP HEMTs increases following exposure to H2. This BVDG shift is nonrecoverable. The increase in BVDG is found to be due to a decrease in the carrier concentration in the extrinsic portion of the device.We provide evidence that H2 reacts with the exposed InAlAs surface in the extrinsic region next to the gate, changing the underlying carrier concentration. Hall measurements of capped and uncapped HEMT samples show that the decrease in sheet carrier concentration can be attributed to a modification of the exposed InAlAs surface. Consistent with this, XPS experiments on uncapped heterostructures give evidence of As loss from the InAlAs surface upon exposure to hydrogen.

Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.

Electrical and optical properties of Zn-In-Sn-O transparent conducting thin films

Indium tin oxide (ITO) is one of the widely used transparent conductive oxides (TCO) for application as transparent electrode in thin film silicon solar cells or thin film transistors owing to its low resistivity and high transparency. Nevertheless, indium is a scarce and expensive element and ITO films require high deposition temperature to achieve good electrical and optical properties. On the other hand, although not competing as ITO, doped Zinc Oxide (ZnO) is a promising and cheaper alternative. Therefore, our strategy has been to deposit ITO and ZnO multicomponent thin films at room temperature by radiofrequency (RF) magnetron co-sputtering in order to achieve TCOs with reduced indium content. Thin films of the quaternary system Zn-In-Sn-O (ZITO) with improved electrical and optical properties have been achieved. The samples were deposited by applying different RF powers to ZnO target while keeping a constant RF power to ITO target. This led to ZITO films with zinc content ratio varying between 0 and 67%. The optical, electrical and morphological properties have been thoroughly studied. The film composition was analysed by X-ray Photoelectron Spectroscopy. The films with 17% zinc content ratio showed the lowest resistivity (6.6 × 10 - 4 Ω cm) and the highest transmittance (above 80% in the visible range). Though X-ray Diffraction studies showed amorphous nature for the films, using High Resolution Transmission Electron Microscopy we found that the microstructure of the films consisted of nanometric crystals embedded in a compact amorphous matrix. The effect of post deposition annealing on the films in both reducing and oxidizing atmospheres were studied. The changes were found to strongly depend on the zinc content ratio in the films.

Optimisation of doped microcrystalline silicon films deposited at very low temperatures by Hot-Wire CVD

In this paper we present new results on doped μc-Si:H thin films deposited by hot-wire chemical vapour deposition (HWCVD) in the very low temperature range (125-275°C). The doped layers were obtained by the addition of diborane or phosphine in the gas phase during deposition. The incorporation of boron and phosphorus in the films and their influence on the crystalline fraction are studied by secondary ion mass spectrometry and Raman spectroscopy, respectively. Good electrical transport properties were obtained in this deposition regime, with best dark conductivities of 2.6 and 9.8 S cm -1 for the p- and n-doped films, respectively. The effect of the hydrogen dilution and the layer thickness on the electrical properties are also studied. Some technological conclusions referred to cross contamination could be deduced from the nominally undoped samples obtained in the same chamber after p- and n-type heavily doped layers.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Top-gate microcrystalline silicon TFTs processed at low temperature (<200ºC)

N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 °C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2-N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it=6.4×10 10 eV -1 cm -2. High field effect mobility, 25 cm 2/V s for electrons and 1.1 cm 2/V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously.

Structure of a-Si:H/a-Si1-xCx:H multilayers deposited in a reactor with automated substrate holder

This paper deals with the structural properties of a-Si:H/a-Si1-xCx: H multilayers deposited by glow-discharge decomposition of SiH4 and SiH4 and CH4 mixtures. The main feature of the rf plasma reactor is an automated substrate holder. The plasma stabilization time and its influence on the multilayer obtained is discussed. A series of a-Si:H/a-Si1-xCx: H multilayers has been deposited and characterized by secondary ion mass spectrometry (SIMS), X-ray diffraction (XRD) and transmission electron microscopy (TEM). No asymmetry between the two types of interface has been observed. The results show that the multilayers present a very good periodicity and low roughness. The difficulty of determining the abruptness of the multilayer at the nanometer scale is discussed.

Extension of the impedance field method to the noise analysis of a semiconductor junction: Analytical approach

We present an analytical procedure to perform the local noise analysis of a semiconductor junction when both the drift and diffusive parts of the current are important. The method takes into account space-inhomogeneous and hot-carriers conditions in the framework of the drift-diffusion model, and it can be effectively applied to the local noise analysis of different devices: n+nn+ diodes, Schottky barrier diodes, field-effect transistors, etc., operating under strongly inhomogeneous distributions of the electric field and charge concentration

Extension of the impedance field method to the noise analysis of a semiconductor junction: Analytical approach

We present an analytical procedure to perform the local noise analysis of a semiconductor junction when both the drift and diffusive parts of the current are important. The method takes into account space-inhomogeneous and hot-carriers conditions in the framework of the drift-diffusion model, and it can be effectively applied to the local noise analysis of different devices: n+nn+ diodes, Schottky barrier diodes, field-effect transistors, etc., operating under strongly inhomogeneous distributions of the electric field and charge concentration

Theory of surface noise under Coulomb correlations between carriers and surface states

We present a theory of the surface noise in a nonhomogeneous conductive channel adjacent to an insulating layer. The theory is based on the Langevin approach which accounts for the microscopic sources of fluctuations originated from trapping¿detrapping processes at the interface and intrachannel electron scattering. The general formulas for the fluctuations of the electron concentration, electric field as well as the current-noise spectral density have been derived. We show that due to the self-consistent electrostatic interaction, the current noise originating from different regions of the conductive channel appears to be spatially correlated on the length scale correspondent to the Debye screening length in the channel. The expression for the Hooge parameter for 1/f noise, modified by the presence of Coulomb interactions, has been derived