Hardness and structure characterization of Ti(6)Al(4)V films produced by reactive magnetron sputtering on a conventional austenitic stainless steel

Ti(6)Al(4)V thin films were grown by magnetron sputtering on a conventional austenitic stainless steel. Five deposition conditions varying both the deposition chamber pressure and the plasma power were studied. Highly textured thin films were obtained, their crystallite size (C) 2008 Elsevier Ltd. All rights reserved.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

Improved effective charge density in MOS capacitors with PECVD SiOxNy dielectric layer obtained at low RF power

In this work SiOxNy films are produced and characterized. Series of samples were deposited by the plasma enhanced chemical vapor deposition (PECVD) technique at low temperatures from silane (SiH4), nitrous oxide (N2O) and helium (He) precursor gaseous mixtures, at different deposition power in order to analyze the effect of this parameter on the films structural properties, on the SiOxNy/Si interface quality and on the SiOxNy effective charge density. In order to compare the film structural properties with the interface (SiOxNy/Si) quality and effective charge density, MOS capacitors were fabricated using these films as dielectric layer. X-ray absorption near-edge spectroscopy (XANES), at the Si-K edge, was utilized to investigate the structure of the films and the material bonding characteristics were analyzed through Fourier transform infrared spectroscopy (FTIR). The MOS capacitors were characterized by low and high frequency capacitance (C-V) measurements, in order to obtain the interface state density (D-it) and the effective charge density (N-ss). An effective charge density linear reduction for decreasing deposition power was observed, result that is attributed to the smaller amount of ions present in the plasma for low RF power. (C) 2008 Elsevier B.V. All rights reserved.

Porous silicon optical cavity structure applied to high sensitivity organic solvent sensor

The present work reports the thermal annealing process, the number of layer and electrochemical process effect in the optical response quality of Bragg and microcavity devices that were applied as organic solvent sensors. These devices have been obtained by using porous silicon (PS) technology. The optical characterization of the Bragg reflector, before annealing, showed a broad photonic band-gap structure with blue shifted and narrowed after annealing process. The electrochemical process used to obtain the PS-based device imposes the limit in the number of layers because of the chemical dissolution effect. The interface roughness minimizations in the devices have been achieved by using the double electrochemical cell setup. The microcavity devices showed to have a good sensibility for organic solvent detection. The thermal annealed device showed better sensibility feature and this result was attributed to passivation of the surface devices. (c) 2007 Elsevier Ltd. All rights reserved.

Impact of SEG on uniaxially strained MuGFET performance

This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L./W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (R(s)) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both R(s) and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEC ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. (C) 2011 Elsevier Ltd. All rights reserved.

Optimized network structure for full-synchronization

A network of Kuramoto oscillators with different natural frequencies is optimized for enhanced synchronizability. All node inputs are normalized by the node connectivity and some important properties of the network Structure are determined in this case: (i) optimized networks present a strong anti-correlation between natural frequencies of adjacent nodes: (ii) this anti-correlation should be as high as possible since the average path length between nodes is maintained as small as in random networks: and (iii) high anti-correlation is obtained without any relation between nodes natural frequencies and the degree of connectivity. We also propose a network construction model with which it is shown that high anti-correlation and small average paths may be achieved by randomly rewiring a fraction of the links of a totally anti-correlated network, and that these networks present optimal synchronization properties. (C) 2008 Elsevier B.V. All rights reserved.

Flatness-based control of a single qubit gate

This work considers the open-loop control problem of steering a two-level quantum system from any initial to any final condition. The model of this system evolves on the state space X = SU(2), having two inputs that correspond to the complex amplitude of a resonant laser field. A symmetry preserving flat output is constructed using a fully geometric construction and quaternion computations. Simulation results of this flatness-based open-loop control are provided.

Experimental Measurement of Water Diffusion through Fine Aggregate Mixtures

The water diffusion attributable to concentration gradients is among the main mechanisms of water transport into the asphalt mixture. The transport of small molecules through polymeric materials is a very complex process, and no single model provides a complete explanation because of the small molecule`s complex internal structure. The objective of this study was to experimentally determine the diffusion of water in different fine aggregate mixtures (FAM) using simple gravimetric sorption measurements. For the purposes of measuring the diffusivity of water, FAMs were regarded as a representative homogenous volume of the hot-mix asphalt (HMA). Fick`s second law is generally used to model diffusion driven by concentration gradients in different materials. The concept of the dual mode diffusion was investigated for FAM cylindrical samples. Although FAM samples have three components (asphalt binder, aggregates, and air voids), the dual mode was an attempt to represent the diffusion process by only two stages that occur simultaneously: (1) the water molecules are completely mobile, and (2) the water molecules are partially mobile. The combination of three asphalt binders and two aggregates selected from the Strategic Highway Research Program`s (SHRP) Materials Reference Library (MRL) were evaluated at room temperature [23.9 degrees C (75 degrees F)] and at 37.8 degrees C (100 degrees F). The results show that moisture uptake and diffusivity of water through FAM is dependent on the type of aggregate and asphalt binder. At room temperature, the rank order of diffusivity and moisture uptake for the three binders was the same regardless of the type of aggregate. However, this rank order changed at higher temperatures, suggesting that at elevated temperatures different binders may be undergoing a different level of change in the free volume. DOI: 10.1061/(ASCE)MT.1943-5533.0000190. (C) 2011 American Society of Civil Engineers.

Structure and properties of an austenitic stainless steel AISI 316L grade ASTM F138 after low temperature plasma nitriding

Austenitic stainless steels cannot be conventionally nitrided at temperatures near 550 degrees C due to the intense precipitation of chromium nitrides in the diffusion zone. The precipitation of chro-mium nitrides increases the hardness but severely impairs corrosion resistance. Plasma nitriding allows introducing nitrogen in the steel at temperatures below 450 degrees C, forming pre-dominantly expanded austenite (gamma(N)), with a crystalline structure best represented by a special triclin-ic lattice, with a very high nitrogen atomic concentration promoting high compressive residual stresses at the surface, increasing substrate hardness from 4 GPa up to 14 GPa on the nitrided case.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.