On the resilience of long cycles in random graphs

In this paper we determine the local and global resilience of random graphs G(n,p) (p >> n(-1)) with respect to the property of containing a cycle of length at least (1 - alpha)n. Roughly speaking, given alpha > 0, we determine the smallest r(g) (G, alpha) with the property that almost surely every subgraph of G = G(n,p) having more than r(g) (G, alpha)vertical bar E(G)vertical bar edges contains a cycle of length at least (1 - alpha)n (global resilience). We also obtain, for alpha < 1/2, the smallest r(l) (G, alpha) such that any H subset of G having deg(H) (v) larger than r(l) (G, alpha) deg(G) (v) for all v is an element of V(G) contains a cycle of length at least (1 - alpha)n (local resilience). The results above are in fact proved in the more general setting of pseudorandom graphs.

Fault current test of a bifilar Bi-2212 bulk coil

A bifilar Bi-2212 bulk coil with parallel shunt resistor was tested under fault current condition using a 3 MVA single-phase transformer in a 220 V-60 Hz line achieving fault current peak of 8 kA. The fault current tests are performed from steady state peak current of 200 A by applying controlled short circuits up to 8 kA varying the time period from one to six cycles. The test results show the function of the shunt resistor providing homogeneous quench behavior of the HTS coil besides its intrinsic stabilizing role. The limiting current ratio achieves a factor 4.2 during 5 cycles without any degradation.

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 mu m CMOS technology, requiring an active area of just 200 mu m x 200 mu m. Experimental results, with a full-scale output current of 700 mu A and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.

Chaotic communication based on the particle-in-a-box electronic circuit

A secure communication system based on the error-feedback synchronization of the electronic model of the particle-in-a-box system is proposed. This circuit allows a robust and simple electronic emulation of the mechanical behavior of the collisions of a particle inside a box, exhibiting rich chaotic behavior. The required nonlinearity to emulate the box walls is implemented in a simple way when compared with other analog electronic chaotic circuits. A master/slave synchronization of two circuits exhibiting a rich chaotic behavior demonstrates the potentiality of this system to secure communication. In this system, binary data stream information modulates the bifurcation parameter of the particle-in-a-box electronic circuit in the transmitter. In the receiver circuit, this parameter is estimated using Pecora-Carroll synchronization and error-feedback synchronization. The performance of the demodulation process is verified through the eye pattern technique applied on the recovered bit stream. During the demodulation process, the error-feedback synchronization presented better performance compared with the Pecora-Carroll synchronization. The application of the particle-in-a-box electronic circuit in a secure communication system is demonstrated.

Modeling and analysis of laminate composite plates with embedded active-passive piezoelectric networks

The objective of this work is to present the finite element modeling of laminate composite plates with embedded piezoelectric patches or layers that are then connected to active-passive resonant shunt circuits, composed of resistance, inductance and voltage source. Applications to passive vibration control and active control authority enhancement are also presented and discussed. The finite element model is based on an equivalent single layer theory combined with a third-order shear deformation theory. A stress-voltage electromechanical model is considered for the piezoelectric materials fully coupled to the electrical circuits. To this end, the electrical circuit equations are also included in the variational formulation. Hence, conservation of charge and full electromechanical coupling are guaranteed. The formulation results in a coupled finite element model with mechanical (displacements) and electrical (charges at electrodes) degrees of freedom. For a Graphite-Epoxy (Carbon-Fibre Reinforced) laminate composite plate, a parametric analysis is performed to evaluate optimal locations along the plate plane (xy) and thickness (z) that maximize the effective modal electromechanical coupling coefficient. Then, the passive vibration control performance is evaluated for a network of optimally located shunted piezoelectric patches embedded in the plate, through the design of resistance and inductance values of each circuit, to reduce the vibration amplitude of the first four vibration modes. A vibration amplitude reduction of at least 10 dB for all vibration modes was observed. Then, an analysis of the control authority enhancement due to the resonant shunt circuit, when the piezoelectric patches are used as actuators, is performed. It is shown that the control authority can indeed be improved near a selected resonance even with multiple pairs of piezoelectric patches and active-passive circuits acting simultaneously. (C) 2010 Elsevier Ltd. All rights reserved.

Thermal characterization of a cross-flow heat exchanger with a new flow arrangement

The objective of the present paper is to thermally characterize a cross-flow heat exchanger featuring a new cross-flow arrangement, which may find application in contemporary refrigeration and automobile industries. The new flow arrangement is peculiar in the sense that it possesses two fluid circuits extending in the form of two tube rows, each with two tube lines. To assess the heat exchanger performance, it is compared against that for the standard two-pass counter-cross-flow arrangement. The two-part comparison is based on the thermal effectiveness and the heat exchanger efficiency for several combinations of the heat capacity rate ratio, C*, and the number of transfer units, NTU. In addition, a third comparison is made in terms of the so-called ""heat exchanger reversibility norm"" (HERN) through the influence of various parameters such as the inlet temperature ratio, T, and the heat capacity rate ratio, C*, for several fixed NTU values. The proposed new flow arrangement delivers higher thermal effectiveness and higher heat exchanger efficiency, resulting in lesser entropy generation over a wide range of C* and NTU values. These metrics are quantified with respect to the arrangement widely used in refrigeration industry due to its high effectiveness, namely, the standard two-pass counter-cross-flow heat exchanger. The new flow arrangement seems to be a promising avenue in situations where cross-flow heat exchangers for single-phase fluid have to be used in refrigeration units. (c) 2009 Elsevier Masson SAS. All rights reserved.

Multimodal passive vibration control of sandwich beams with shunted shear piezoelectric materials

This work presents a performance analysis of multimodal passive vibration control of a sandwich beam using shear piezoelectric materials, embedded in a sandwich beam core, connected to independent resistive shunt circuits. Shear piezoelectric actuators were recently shown to be more interesting for higher frequencies and stiffer structures. In particular, for shunted damping, it was shown that equivalent material loss factors of up to 31% can be achieved by optimizing the shunt circuit. In the present work, special attention is given to the design of multimodal vibration control through independent shunted shear piezoelectric sensors. In particular, a parametric analysis is performed to evaluate optimal configurations for a set of modes to be damped. Then, a methodology to evaluate the modal damping resulting from each shunted piezoelectric sensor is presented using the modal strain energy method. Results show that modal damping factors of 1%-2% can be obtained for three selected vibration modes.

Fuzzy computational control for real Chua circuit

We preserit a computational procedure to control art experimental chaotic system by applying the occasional proportional feedback (OPF) method. The method implementation uses the fuzzy theory to relate the variable correction to the necessary adjustment in the control parameter. As an application We control the chaotic attractors of the Chua circuit. We present file developed circuits and algorithms to implement this control in real time. To simplify the used procedure, we use it low resolution analog to digital converter compensated for a lowpass filter that facilitates similar applications to control other systems. (C) 2007 Elsevier Ltd. All rights reserved.

Feasibility of Electronic Tap-Changing Stabilizers for Medium Voltage Lines-Precedents and New Configurations

Thyristor-based onload tap-changing ac voltage stabilizers are cheap and robust. They have replaced most mechanical tap-changers in low voltage applications from 300 VA to 300 M. Nevertheless, this replacement hardily applies to tap-changers associated to transformers feeding medium-voltage lines (typically 69 kV primary, 34.5 kV line, 10 MVA) which need periodical maintenance of contacts and oil. The Electric Power Research Institute (EPRI) has studied the feasibility of this replacement. It detected economical problems derived from the need for series association of thyristors to manage the high voltages involved, and from the current overload developed under line fault. The paper reviews the configurations used in that field and proposes new solutions, using a compensating transformer in the main circuit and multi-winding coils in the commutating circuit, with reduced overload effect and no series association of thyristors, drastically decreasing their number and rating. The stabilizer can be installed at any point of the line and the electronic circuit can be fixed to ground. Subsequent works study and synthesize several commutating circuits in detail.

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

Modeling and Filtering Double-Frequency Jitter in One-Way Master-Slave Chain Networks

One-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by their phase detectors appears as an impairment to the performance of the clock recovering process found in communication systems and instrumentation applications. A nonlinear model for OWMS chain networks with P + 1 order PLLs as slave nodes is presented, considering the DFJ. Since higher order filters are more effective in filtering DFJ, the synchronous state stability conditions for an OWMS chain network with third-order nodes are derived, relating the loop gain and the filter coefficients. By using these conditions, design examples are discussed.

Using bifurcations in the determination of lock-in ranges for third-order phase-locked loops

Transmission and switching in digital telecommunication networks require distribution of precise time signals among the nodes. Commercial systems usually adopt a master-slave (MS) clock distribution strategy building slave nodes with phase-locked loop (PLL) circuits. PLLs are responsible for synchronizing their local oscillations with signals from master nodes, providing reliable clocks in all nodes. The dynamics of a PLL is described by an ordinary nonlinear differential equation, with order one plus the order of its internal linear low-pass filter. Second-order loops are commonly used because their synchronous state is asymptotically stable and the lock-in range and design parameters are expressed by a linear equivalent system [Gardner FM. Phaselock techniques. New York: John Wiley & Sons: 1979]. In spite of being simple and robust, second-order PLLs frequently present double-frequency terms in PD output and it is very difficult to adapt a first-order filter in order to cut off these components [Piqueira JRC, Monteiro LHA. Considering second-harmonic terms in the operation of the phase detector for second order phase-locked loop. IEEE Trans Circuits Syst [2003;50(6):805-9; Piqueira JRC, Monteiro LHA. All-pole phase-locked loops: calculating lock-in range by using Evan`s root-locus. Int J Control 2006;79(7):822-9]. Consequently, higher-order filters are used, resulting in nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on parameters combinations, can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing synchronization ranges. In this work, we consider a second-order Sallen-Key loop filter [van Valkenburg ME. Analog filter design. New York: Holt, Rinehart & Winston; 1982] implying a third order PLL The resulting lock-in range of the third-order PLL is determined by two bifurcation conditions: a saddle-node and a Hopf. (C) 2008 Elsevier B.V. All rights reserved.

Optimization of the Topology of Electric Energy Distribution Networks by Using Algorithm Inspired on Ant Behaviors

An algorithm inspired on ant behavior is developed in order to find out the topology of an electric energy distribution network with minimum power loss. The algorithm performance is investigated in hypothetical and actual circuits. When applied in an actual distribution system of a region of the State of Sao Paulo (Brazil), the solution found by the algorithm presents loss lower than the topology built by the concessionary company.