37 resultados para CMOS integrated circuits


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In disorders such as sleep apnea, sleep is fragmented with frequent EEG-arousal (EEGA) as determined via changes in the sleep-electroencephalogram. EEGA is a poorly understood, complicated phenomenon which is critically important in studying the mysteries of sleep. In this paper we study the information flow between the left and right hemispheres of the brain during the EEGA as manifested through inter-hemispheric asynchrony (IHA) of the surface EEG. EEG data (using electrodes A1/C4 and A2/C3 of international 10-20 system) was collected from 5 subjects undergoing routine polysomnography (PSG). Spectral correlation coefficient (R) was computed between EEG data from two hemispheres for delta-delta(0.5-4 Hz), theta-thetas(4.1-8 Hz), alpha-alpha(8.1-12 Hz) & beta-beta(12.1-25 Hz) frequency bands, during EEGA events. EEGA were graded in 3 levels as (i) micro arousals (3-6 s), (ii) short arousals (6.1-10 s), & (iii) long arousals (10.1-15 s). Our results revealed that in beta band, IHA increases above the baseline after the onset of EEGA and returns to the baseline after the conclusion of event. Results indicated that the duration of EEGA events has a direct influence on the onset of IHA. The latency (L) between the onset of arousals and IHA were found to be L=2plusmn0.5 s (for micro arousals), 4plusmn2.2 s (short arousals) and 6.5plusmn3.6 s (long arousals)

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In this paper, we propose an algorithm for partitioning parameterized orthogonal polygons into rectangles. The algorithm is based on the plane-sweep technique and can be used for partitioning polygons which contain holes. The input to the algorithm consists of the contour of a parameterized polygon to be partitioned and the constraints for those parameters which reside in the contour. The algorithm uses horizontal cuts only and generates a minimum number of rectangles whose union is the original orthogonal polygon. The proposed algorithm can be used as the basis to build corner stitching data structure for parameterized VLSI layouts and has been implemented in Java programming language. Copyright © 2010 ACM, Inc.

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