The effects of TMS over dorsolateral prefrontal cortex on trans-saccadic memory of multiple objects

Humans typically make several rapid eye movements (saccades) per second. It is thought that visual working memory can retain and spatially integrate three to four objects or features across each saccade but little is known about this neural mechanism. Previously we showed that transcranial magnetic stimulation (TMS) to the posterior parietal cortex and frontal eye fields degrade trans-saccadic memory of multiple object features (Prime, Vesia, & Crawford, 2008, Journal of Neuroscience, 28(27), 6938-6949; Prime, Vesia, & Crawford, 2010, Cerebral Cortex, 20(4), 759-772.). Here, we used a similar protocol to investigate whether dorsolateral prefrontal cortex (DLPFC), an area involved in spatial working memory, is also involved in trans-saccadic memory. Subjects were required to report changes in stimulus orientation with (saccade task) or without (fixation task) an eye movement in the intervening memory interval. We applied single-pulse TMS to left and right DLPFC during the memory delay, timed at three intervals to arrive approximately 100ms before, 100ms after, or at saccade onset. In the fixation task, left DLPFC TMS produced inconsistent results, whereas right DLPFC TMS disrupted performance at all three intervals (significantly for presaccadic TMS). In contrast, in the saccade task, TMS consistently facilitated performance (significantly for left DLPFC/perisaccadic TMS and right DLPFC/postsaccadic TMS) suggesting a dis-inhibition of trans-saccadic processing. These results are consistent with a neural circuit of trans-saccadic memory that overlaps and interacts with, but is partially separate from the circuit for visual working memory during sustained fixation.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Control of leaky-mode propagation and radiation properties in hybrid dielectric-waveguide printed-circuit technology: Experimental results

Experimental results are presented to show how a planar circuit, printed on a laterally shielded dielectric waveguide, can induce and control the radiation from a leaky-mode. By studying the leaky-mode complex propagation constant, a desired radiation pattern can be synthesized, controlling the main radiation characteristics (pointing direction, beamwidth, sidelobes level) for a given frequency, This technique leads to very flexible and original leaky-wave antenna designs. The experiments show to be in very good agreement with the leaky-mode theory.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

Implementation of a network flow lookup circuit for next-generation packet classifiers

This paper presents a lookup circuit with advanced memory techniques and algorithms that examines network packet headers at high throughput rates. Hardware solutions and test scenarios are introduced to evaluate the proposed approach. The experimental results show that the proposed lookup circuit is able to achieve at least 39 million packet header lookups per second, which facilitates the application of next-generation stateful packet classifications at beyond 20Gbps internet traffic throughput rates.

Design and analysis of matching circuit architectures for a closest match lookup

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. © 2006 IEEE.

Susceptibility to environmentally induced cracking of laser-welded NiTi wires in Hanks’ solution at open-circuit potential

In the present study the tensile and super-elastic behaviours of laser-welded NiTi wires in Hanks’ solution at open-circuit potential (OCP) were investigated using tensile and cyclic slow-strain-rate tests (SSRT). In comparison with NiTi weldment tested in oil (non-corrosive environment), the weldment in Hanks’ solution suffered from obvious degradation in the tensile properties as evidenced by lower tensile strength, reduced maximum elongation, and a brittle fracture mode. Moreover, a larger residual strain was observed in the weldment after stress–strain cycles in Hanks’ solution. In addition to the microstructural defects resulting from the welding process, the inferior tensile and super-elastic behaviours of the NiTi weldment in Hanks’ solution could be attributed to the trapping of a large amount of hydrogen in the weld zone and heat-affected zone.

Identification of CO adsorbed at Ru and Pt sites on a polycrystalline Pt/Ru electrode and the observation of their oxidation and free interchange under open circuit conditions

The spontaneous oxidation of CO adsorbates on a Pt electrode modified by Ru under open circuit (OC) conditions in perchloric acid solution has been followed, for the first time, using in situ FTIR spectroscopy, and the dynamics of the surface processes taking place have been elucidated. The IR data show that adsorbed CO present on both the Ru and Pt domains and can be oxidized by the oxygen-containing adlayer on the Ru in a chemical process to produce CO under OC conditions. There is a free exchange of CO is between the Ru and Pt sites. Oxidation of CO may take place at the edges of the Ru islands, but CO is transfer, at least on the time scale of these experiments, allows the two different populations to maintain equilibrium. Oxidation is limited in this region by the rate of supply of oxygen to die surface of the catalyst. A mechanism is postulated to explain the observed behavior.