Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

VLSI processor for high-performance arithmetic computations

A high performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform one or more of these operations. The throughput rate for each operation is the same and is wordlength independent. This is achieved using redundant arithmetic. With current CMOS technology, throughput rates in excess of 80 million operations per second are expected.

Cognitive and task-related EEG correlates of arithmetic performance in adolescents

Cognitive and neurophysiological correlates of arithmetic calculation, concepts, and applications were examined in 41 adolescents, ages 12-15 years. Psychological and task-related EEG measures which correctly distinguished children who scored low vs. high (using a median split) in each arithmetic subarea were interpreted as indicative of processes involved. Calculation was related to visual-motor sequencing, spatial visualization, theta activity measured during visual-perceptual and verbal tasks at right- and left-hemisphere locations, and right-hemisphere alpha activity measured during a verbal task. Performance on arithmetic word problems was related to spatial visualization and perception, vocabulary, and right-hemisphere alpha activity measured during a verbal task. Results suggest a complex interplay of spatial and sequential operations in arithmetic performance, consistent with processing model concepts of lateralized brain function.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

A hybrid harmony search with arithmetic crossover operation for economic dispatch

Economic dispatch (ED) problems often exhibit non-linear, non-convex characteristics due to the valve point effects. Further, various constraints and factors, such as prohibited operation zones, ramp rate limits and security constraints imposed by the generating units, and power loss in transmission make it even more challenging to obtain the global optimum using conventional mathematical methods. Meta-heuristic approaches are capable of solving non-linear, non-continuous and non-convex problems effectively as they impose no requirements on the optimization problems. However, most methods reported so far mainly focus on a specific type of ED problems, such as static or dynamic ED problems. This paper proposes a hybrid harmony search with arithmetic crossover operation, namely ACHS, for solving five different types of ED problems, including static ED with valve point effects, ED with prohibited operating zones, ED considering multiple fuel cells, combined heat and power ED, and dynamic ED. In this proposed ACHS, the global best information and arithmetic crossover are used to update the newly generated solution and speed up the convergence, which contributes to the algorithm exploitation capability. To balance the exploitation and exploration capabilities, the opposition based learning (OBL) strategy is employed to enhance the diversity of solutions. Further, four commonly used crossover operators are also investigated, and the arithmetic crossover shows its efficiency than the others when they are incorporated into HS. To make a comprehensive study on its scalability, ACHS is first tested on a group of benchmark functions with a 100 dimensions and compared with several state-of-the-art methods. Then it is used to solve seven different ED cases and compared with the results reported in literatures. All the results confirm the superiority of the ACHS for different optimization problems.

Number comparison and number ordering as predictors of arithmetic performance in adults: Exploring the link between the two skills, and investigating the question of domain-specificity.

Recent evidence has highlighted the important role that number ordering skills play in arithmetic abilities (e.g., Lyons & Beilock, 2011). In fact, Lyons et al. (2014) demonstrated that although at the start of formal mathematics education number comparison skills are the best predictors of arithmetic performance, from around the age of 10, number ordering skills become the strongest numerical predictors of arithmetic abilities. In the current study we demonstrated that number comparison and ordering skills were both significantly related to arithmetic performance in adults, and the effect size was greater in the case of ordering skills. Additionally, we found that the effect of number comparison skills on arithmetic performance was partially mediated by number ordering skills. Moreover, performance on comparison and ordering tasks involving the months of the year was also strongly correlated with arithmetic skills, and participants displayed similar (canonical or reverse) distance effects on the comparison and ordering tasks involving months as when the tasks included numbers. This suggests that the processes responsible for the link between comparison and ordering skills and arithmetic performance are not specific to the domain of numbers. Finally, a factor analysis indicated that performance on comparison and ordering tasks loaded on a factor which included performance on a number line task and self-reported spatial thinking styles. These results substantially extend previous research on the role of order processing abilities in mental arithmetic.

Queen-worker conflict over male production and sex ratio in a facultatively polyandrous bumble bee, Bombus hypnorum: the consequences of nest usurpation.

Evolutionary conflicts among social hymenopteran nestmates are theoretically likely to arise over the production of males and the sex ratio. Analysis of these conflicts has become an important focus of research into the role of kin selection in shaping social traits of hymenopteran colonies. We employ microsatellite analysis of nestmates of one social hymenopteran, the primitively eusocial and monogynous bumblebee Bombus hypnorum, to evaluate these conflicts. In our 14 study colonies, B. hypnorum queens mated between one and six times (arithmetic mean 2.5). One male generally predominated, fathering most of the offspring, thus the effective number of matings was substantially lower (1–3.13; harmonic mean 1.26). In addition, microsatellite analysis allowed the detection of alien workers, those who could not have been the offspring of the queen, in approximately half the colonies. Alien workers within the same colony were probably sisters. Polyandry and alien workers resulted in high variation among colonies in their sociogenetic organization. Genetic data were consistent with the view that all males (n = 233 examined) were produced by a colony’s queen. Male parentage was therefore independent of the sociogenetic organization of the colony, suggesting that the queen, and not the workers, was in control of the laying of male-destined eggs. The population-wide sex ratio (fresh weight investment ratio) was weakly female biased. No evidence for colony-level adaptive sex ratio biasing could be detected.