Rapid design of application specific FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterized commutator and processor blocks are cascaded to implement the computations required in many important FFT signal flow graphs. In addition, it is shown how the use of a digital serial data organization can be used to produce systems that offer 100% processor utilization along with reductions in storage requirements. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with ones created using manual methods but with significant reductions in design times.

Synthesizable FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

Synthesisable FFT cores

Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% processor utilisation with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

DESIGNING VLSI SIGNAL PROCESSING CHIPS USING DATA DEPENDENCE GRAPHS.

The highly structured nature of many digital signal processing operations allows these to be directly implemented as regular VLSI circuits. This feature has been successfully exploited in the design of a number of commercial chips, some examples of which are described. While many of the architectures on which such chips are based were originally derived on heuristic basis, there is an increasing interest in the development of systematic design techniques for the direct mapping of computations onto regular VLSI arrays. The purpose of this paper is to show how the the technique proposed by Kung can be readily extended to the design of VLSI signal processing chips where the organisation of computations at the level of individual data bits is of paramount importance. The technique in question allows architectures to be derived using the projection and retiming of data dependence graphs.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

Data-driven optimal filtering for phase and frequency of noisy oscillations: Application to vortex flow metering

A method for measuring the phase of oscillations from noisy time series is proposed. To obtain the phase, the signal is filtered in such a way that the filter output has minimal relative variation in the amplitude over all filters with complex-valued impulse response. The argument of the filter output yields the phase. Implementation of the algorithm and interpretation of the result are discussed. We argue that the phase obtained by the proposed method has a low susceptibility to measurement noise and a low rate of artificial phase slips. The method is applied for the detection and classification of mode locking in vortex flow meters. A measure for the strength of mode locking is proposed.

Detection of improper installation from the sensor signal of vortex flowmeters

Effects of inappropriate installation can bias the measurements of flowmeters. For vortex flowmeters, a method is proposed to detect inappropriate installation of the flowmeter from the oscillatory signal of the vortex sensor. The method is based on assuming the process of vortex generation to be a generic, noisy, nonlinear oscillation, describable by a noisy Stuart-Landau equation, with a corresponding sensor signal that also contains higher harmonic excitations. By making use of the scaling properties of the Navier-Stokes Equation, the method was designed to be robust with respect to uncertainties in the fluid properties. The diagnostic functionality is demonstrated on measurement data. In the experiments, installation effects that lead to more than 0.5% error in the output of the flowmeter could clearly be detected. (C) 2003 Elsevier Ltd. All rights reserved.

Signal and variability within a Holocene peat bog - Chronological uncertainties of pollen, macrofossil and fungal proxies

A single raised bog from the eastern Netherlands has been repeatedly analysed and ¹⁴C dated over the past few decades. Here we assess the within-site variability of fossil proxy data through comparing the regional
pollen, macrofossils and non-pollen palynomorphs of four of these profiles. High-resolution chronologies were obtained using ¹⁴C dating and Bayesian age-depth modelling. Where chronologies of profiles overlap, proxy curves are compared between the profiles using greyscale graphs that visualise chronological uncertainties. Even at this small spatial scale, there is considerable variability of the fossil proxy curves. Implications regarding signal (climate) and noise (internal dynamics) of the different types of fossil proxies are discussed. Single cores are of limited value for reconstructing centennial-scale climate change, and only by combining multiple cores and proxies can we obtain a reliable understanding of past environmental change and possible forcing factors (e.g., solar variability).

Use of data dependence graphs in the design of bit-level systolic arrays

The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S. Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.

Sustained activation of XBP1 splicing leads to endothelial apoptosis and atherosclerosis development in response to disturbed flow

X-box binding protein 1 (XBP1) is a key signal transducer in endoplasmic reticulum stress response, and its potential role in the atherosclerosis development is unknown. This study aims to explore the impact of XBP1 on maintaining endothelial integrity related to atherosclerosis and to delineate the underlying mechanism. We found that XBP1 was highly expressed at branch points and areas of atherosclerotic lesions in the arteries of ApoE(-/-) mice, which was related to the severity of lesion development. In vitro study using human umbilical vein endothelial cells (HUVECs) indicated that disturbed flow increased the activation of XBP1 expression and splicing. Overexpression of spliced XBP1 induced apoptosis of HUVECs and endothelial loss from blood vessels during ex vivo cultures because of caspase activation and down-regulation of VE-cadherin resulting from transcriptional suppression and matrix metalloproteinase-mediated degradation. Reconstitution of VE-cadherin by Ad-VEcad significantly increased Ad-XBP1s-infected HUVEC survival. Importantly, Ad-XBP1s gene transfer to the vessel wall of ApoE(-/-) mice resulted in development of atherosclerotic lesions after aorta isografting. These results indicate that XBP1 plays an important role in maintaining endothelial integrity and atherosclerosis development, which provides a potential therapeutic target to intervene in atherosclerosis.

Analysis of Load Impact on Small-signal Stability based on Load Active Power Sensitivity

While load flow conditions vary with different loads, the small-signal stability of the entire system is closely related with to the locations, capacities and models of loads. In this paper, load impacts with different capacities and models on the small-signal stability are analysed. In the real large-scale power system case, the load sensitivity which denotes the sensitivity of the eigenvalue with respect to the load active power is introduced and applied to rank the loads. The loads with high sensitivity are also considered.

Automated, high performance, flow-through chemiluminescence microarray for the multiplexed detection of phycotoxins

A novel multiplexed immunoassay for the analysis of phycotoxins in shellfish samples has been developed. Therefore, a regenerable chemiluminescence (CL) microarray was established which is able to analyze automatically three different phycotoxins (domoic acid (DA), okadaic acid (OA) and saxitoxin (STX)) in parallel on the analysis platform MCR3. As a test format an indirect competitive immunoassay format was applied. These phycotoxins were directly immobilized on an epoxy-activated PEG chip surface. The parallel analysis was enabled by the simultaneous addition of all analytes and specific antibodies on one microarray chip. After the competitive reaction, the CL signal was recorded by a CCD camera. Due to the ability to regenerate the toxin microarray, internal calibrations of phycotoxins in parallel were performed using the same microarray chip, which was suitable for 25 consecutive measurements. For the three target phycotoxins multi-analyte calibration curves were generated. In extracted shellfish matrix, the determined LODs for DA, OA and STX with values of 0.5±0.3 µg L(-1), 1.0±0.6 µg L(-1), and 0.4±0.2 µg L(-1) were slightly lower than in PBS buffer. For determination of toxin recoveries, the observed signal loss in the regeneration was corrected. After applying mathematical corrections spiked shellfish samples were quantified with recoveries for DA, OA, and STX of 86.2%, 102.5%, and 61.6%, respectively, in 20 min. This is the first demonstration of an antibody based phycotoxin microarray.

Small Signal Stability Performance of Power System during High Penetration of Wind Generation

The small signal stability of interconnected power systems is one of the important aspects that need to be investigated since the oscillations caused by this kind of instability have caused many incidents. With the increasing penetration of wind power in the power system, particularly doubly fed induction generator (DFIG), the impact on the power system small signal stability performance should be fully investigated. Because the DFIG wind turbine integration is through a fast action converter and associated control, it does not inherently participate in the electromechanical small signal oscillation. However, it influences the small signal stability by impacting active power flow paths in the network and replacing synchronous generators that have power system stabilizer (PSS). In this paper, the IEEE 39 bus test system has been used in the analysis. Furthermore, four study cases and several operation scenarios have been conducted and analysed. The selective eigenvalue Arnoldi/lanczos's method is used to obtain the system eigenvalue in the range of frequency from 0.2 Hz to 2 Hz which is related to electromechanical oscillations. Results show that the integration of DFIG wind turbines in a system during several study cases and operation scenarios give different influence on small signal stability performance.