Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Perovskite lead zirconium titanate nanorings: Towards nanoscale ferroelectric

Rings of perovskite lead zirconium titanate (PZT) with internal diameters down to similar to 5 nm and ring thicknesses of similar to 5-10 nm have been fabricated and structurally, crystallographically, and chemically characterized using an analytical transmission electron microscope. Ring fabrication involved conformal solution deposition of a thin layer of PZT on the inside of a thin film of anodized aluminum oxide nanopores, and subsequent sectioning of the coated pores perpendicular to their cylinder axes. Although the starting solution used for the solution deposition was made from morphotropic phase boundary PZT, the nanorings were found to be on the zirconium-rich side of the PZT phase diagram. Nevertheless, coatings were found to be of perovskite crystallography. The dimensions of these nanorings are such that they have the potential to demonstrate polarization vortices, as modeled by Naumov [Nature (London) 432, 737 (2004)], and moreover represent the perfect morphology to allow vortex alignment and the creation of the ferroelectric "solenoid" as modeled by Gorbatsevich and Kopaev [Ferroelectrics 161, 321 (1994)].

Transport in nanoscale systems: the microcanonical versus grand-canonical picture

We analyse a picture of transport in which two large but finite charged electrodes discharge across a nanoscale junction. We identify a functional whose minimization, within the space of all bound many-body wavefunctions, defines an instantaneous steady state. We also discuss factors that favour the onset of steady-state conduction in such systems, make a connection with the notion of entropy, and suggest a novel source of steady-state noise. Finally, we prove that the true many-body total current in this closed system is given exactly by the one-electron total current, obtained from time-dependent density-functional theory.

Power dissipation in nanoscale conductors: classical, semi-classical and quantum dynamics

Modelling Joule heating is a difficult problem because of the need to introduce correct correlations between the motions of the ions and the electrons. In this paper we analyse three different models of current induced heating (a purely classical model, a fully quantum model and a hybrid model in which the electrons are treated quantum mechanically and the atoms are treated classically). We find that all three models allow for both heating and cooling processes in the presence of a current, and furthermore the purely classical and purely quantum models show remarkable agreement in the limit of high biases. However, the hybrid model in the Ehrenfest approximation tends to suppress heating. Analysis of the equations of motion reveals that this is a consequence of two things: the electrons are being treated as a continuous fluid and the atoms cannot undergo quantum fluctuations. A means for correcting this is suggested.

Power dissipation in nanoscale conductors

A previous tight-binding model of power dissipation in a nanoscale conductor under an applied bias is extended to take account of the local atomic topology and the local electronic structure. The method is used to calculate the power dissipated at every atom in model nanoconductor geometries: a nanoscale constriction, a one-dimensional atomic chain between two electrodes with a resonant double barrier, and an irregular nanowire with sharp corners. The local power is compared with the local current density and the local density of states. A simple relation is found between the local power and the current density in quasiballistic geometries. A large enhancement in the power at special atoms is found in cases of resonant and anti-resonant transmission. Such systems may be expected to be particularly unstable against current-induced modifications.

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Nanoscale ferroelectrics machined from single crystals

This paper summarises some of the most recent work that has been done on nanoscale ferroelectrics as a result of a joint collaborative research effort involving groups in Queen's University Belfast, the University of Cambridge and the University of St. Andrews. Attempts have been made to observe fundamental effects of reduced size, and increasing morphological complexity, on ferroelectric behaviour by studying the functional response and domain characteristics in nanoscale single crystal material, whose size and morphology have been defined by Focused Ion Beam (FIB) patterning. This approach to nanoshape fabrication has allowed the following broad statements to be made: (i) in single crystal BaTiO3 sheets, permittivity and phase transition behaviour is not altered from that of bulk material down to a thickness of similar to 75 nm; (ii) in single crystal BaTiO3 sheets and nanowires changes in observed domain morphologies are consistent with large scale continuum modeling.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Ferroelectrics at the Nanoscale

There are several factors which make the investigation and understanding of nanoscale ferroelectrics particularly timely and important. Firstly, there is a market pressure, primarily from the electronics industry, to integrate ferroelectrics into devices with progressive decreases in size and increases in morphological complexity. This is perhaps best illustrated through the roadmaps for product development in FeRAM (Ferroelectric Randorn Access Memory) where the need for increases in bit density will require a move from 2D planar capacitor structures to 3D trenched capacitors in the next few years. Secondly, there is opportunity for novel exploration, as it is only relatively recently that developments in thin film growth of complex oxides, self-assembly techniques and high-resolution 'top-down' patterning have converged to allow the fabrication of isolated and well-defined ferroelectric nanoshapes, the properties of which are not known. Thirdly, there is an expectation that the behaviour of small scale ferroelectrics will be different from bulk, as this group of functional materials is highly sensitive to boundary/surface conditions, which are expected to dominate the overall response when sizes are reduced into the nanoscale regime. This feature article attempts to introduce some of the current areas of discovery and debate surrounding studies on ferroelectrics at the nanoscale. The focus is directed primarily at the search for novel size-related properties and behaviour which are not necessarily observed in bulk.

Settling the ‘‘Dead Layer’’ Debate in Nanoscale Capacitors

Permittivity peaks in single crystal thin film capacitors are strongly suppressed compared to bulk in the case of Pt/SrTiO(3)/Pt, but are relatively unaffected in Pt/BaTiO(3)/Pt structures. This is consistent with the recent suggestion that subtle variations in interfacial bonding between the dielectric and electrode are critical in determining the presence or absence of inherent dielectric "dead layers".

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.