Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.

Agitating for a design and regeneration agenda in a postconflict city: the case of Belfast

Introduction

Belfast has been a focus of academic attention for the last forty years with most interest centred on various aspects of ‘the Troubles’. Where there has been interest in the built environment, it has largely been about how the ‘security situation’ impacted directly on architecture and on the design and layout of social housing. This paper seeks to go beyond this to explore how the political- administrative culture of ‘the Troubles’ interacted with ‘normal’ market forces to shape the central area of the city, and to consider the responses of a recently formed activist group, known as the Forum for Alternative Belfast (hereafter referred to as the Forum). The paper is written by three of the directors of the Forum.1 Moreover, the empirical research presented here was undertaken by the Forum as part of a campaign to address issues relating to the design, layout and quality of Belfast’s built environment. In the longstanding tradition of participant observation working within an action-research paradigm, the participants have attempted to offer an account that is evidentially and purposefully selfcritical and reflective. It is of course recognised that while this approach offers many positive attributes, such as phenomenological access through immersion in the project, it also has the potential to bring compromise on research detachment and objectivity.2 To address the latter, the authors have attempted
to avoid polemical argument, and to support claims with primary or secondary research evidence. The authors also acknowledge that action-research has a chequered history; however, they would argue
that their approach is faithful to a concept that sees ‘research’ defined as understanding and ‘action’ defined as seeking change. The Forum’s very purpose is to seek change, but to do this requires evidence, collaboration and demonstration. And in this sense, it is a learning process for all participants, including the research activists, government officials, community organisations and students. The authors also recognise the complexity of factors that affect urban management and change, particularly in a city such as Belfast, which has had to cope with political violence for over thirty years. And they appreciate that in the context of conflict, governance is skewed to cope with political realities. Hamdi reminds us, however, that in practice there is an ‘important dialectic between top-down planning, with its formal and designed laws and structures, and bottom-up selforganizing collectivism—those “quantum and emergent systems” which Jane Jacobs argued long ago give cities their life and order.’3

Design and Practice in Architectural Theory Education

Benefiting from design in theory learning is not common in architecture schools. The general practice is to design in studio and to theorise in lectures. In the undergraduate module History and Theory in Architecture II at Queen’s University Belfast, students attend interactive lectures, participate in reading group discussions, design TextObjects, and write essays. TextObjects contain textual, audio and/or graphic representations that highlight a single concept or a complex set of issues derived from readings. Students experiment with diverse media, such as filmmaking, photography, and graphic design, some of which they experience for the first time. Lectures and readings revolve around theories of architectural representation, media and communication, which are practiced through TextObjects. This is a new way to link theory and practice in architectural education. Through action research, this study analyses this innovative teaching method called TextObject, which brings design and practice into architectural theory education to stimulate students towards critical thinking. The pedagogical research of architectural theoretician Necdet Teymur (1992, 1996, 2002) underlies the study.

Design and test of a bit parallel 2nd order IIR filter structure

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.

Design and implementation of the symmetrically extended 2-D wavelet transform

The inclusion of the Discrete Wavelet Transform in the JPEG-2000 standard has added impetus to the research of hardware architectures for the two-dimensional wavelet transform. In this paper, a VLSI architecture for performing the symmetrically extended two-dimensional transform is presented. This architecture conforms to the JPEG-2000 standard and is capable of near-optimal performance when dealing with the image boundaries. The architecture also achieves efficient processor utilization. Implementation results based on a Xilinx Virtex-2 FPGA device are included.

Design and Implementation of a Measurement-Based Policy-Driven Resource Management Framework For Converged Networks

This paper presents the design and implementation of a measurement-based QoS and resource management framework, CNQF (Converged Networks’ QoS Management Framework). CNQF is designed to provide unified, scalable QoS control and resource management through the use of a policy-based network
management paradigm. It achieves this via distributed functional entities that are deployed to co-ordinate the resources of the transport network through centralized policy-driven decisions supported by measurement-based control architecture. We present the CNQF architecture, implementation of the
prototype and validation of various inbuilt QoS control mechanisms using real traffic flows on a Linux-based experimental test bed.

Two-Way Relaying Networks with Wireless Power Transfer: Policies Design and Throughput Analysis

This paper exploits an amplify-and-forward (AF) two-way relaying network (TWRN), where an energy constrained relay node harvests energy with wireless power transfer. Two bidirectional protocols, multiple access broadcast (MABC) protocol and time division broadcast (TDBC) protocol, are considered. Three wireless power transfer policies, namely, 1) dual-source (DS) power transfer; 2) single-fixed-source (SFS) power transfer; and 3) single-best-source (SBS) power transfer are proposed and well-designed based on time switching receiver architecture. We derive analytical expressions to determine the throughput both for delay-limited transmission and delay-tolerant transmission. Numerical results corroborate our analysis and show that MABC protocol achieves a higher throughput than TDBC protocol. An important observation is that SBS policy offers a good tradeoff between throughput and power.

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

In this paper, we have developed a low-complexity algorithm for epileptic seizure detection with a high degree of accuracy. The algorithm has been designed to be feasibly implementable as battery-powered low-power implantable epileptic seizure detection system or epilepsy prosthesis. This is achieved by utilizing design optimization techniques at different levels of abstraction. Particularly, user-specific critical parameters are identified at the algorithmic level and are explicitly used along with multiplier-less implementations at the architecture level. The system has been tested on neural data obtained from in-vivo animal recordings and has been implemented in 90nm bulk-Si technology. The results show up to 90 % savings in power as compared to prevalent wavelet based seizure detection technique while achieving 97% average detection rate. Copyright 2010 ACM.

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.