VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform
| Data(s) |
27/03/2002
|
|---|---|
| Resumo |
<p>This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.</p> |
| Identificador |
http://www.scopus.com/inward/record.url?scp=84960882691&partnerID=8YFLogxK |
| Idioma(s) |
eng |
| Publicador |
European Signal Processing Conference, EUSIPCO |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
McCanny , P , McCanny , J & Masud , S 2002 , VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform . in European Signal Processing Conference . vol. 3 , 7072288 , European Signal Processing Conference, EUSIPCO , Toulouse , pp. 51 , 11th European Signal Processing Conference, EUSIPCO 2002 , Toulouse , France , 3-6 September . |
| Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1711 #Signal Processing #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
| Tipo |
contributionToPeriodical |
