Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.

Physical modelling of millimetre wave signal reflection from forward biased PIN diodes

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the i-region. The study is conducted using device level simulation of SOI and bulk PIN diodes and reflection modelling based on the Drude conduction model. We examined five diode lengths (60–140 µm) and seven diode thicknesses (4–100 µm). Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100 GHz operation. It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100 GHz. Thinner devices consume less DC power, but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes.

An efficient feature selection method for mobile devices with application to activity recognition

This paper presents a feature selection method for data classification, which combines a model-based variable selection technique and a fast two-stage subset selection algorithm. The relationship between a specified (and complete) set of candidate features and the class label is modelled using a non-linear full regression model which is linear-in-the-parameters. The performance of a sub-model measured by the sum of the squared-errors (SSE) is used to score the informativeness of the subset of features involved in the sub-model. The two-stage subset selection algorithm approaches a solution sub-model with the SSE being locally minimized. The features involved in the solution sub-model are selected as inputs to support vector machines (SVMs) for classification. The memory requirement of this algorithm is independent of the number of training patterns. This property makes this method suitable for applications executed in mobile devices where physical RAM memory is very limited. An application was developed for activity recognition, which implements the proposed feature selection algorithm and an SVM training procedure. Experiments are carried out with the application running on a PDA for human activity recognition using accelerometer data. A comparison with an information gain based feature selection method demonstrates the effectiveness and efficiency of the proposed algorithm.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on Insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100V and average leakage current densities at 70 V were only 55 nA/ sq cm. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45x1011cn-2 for a dose of 2.7Mrad

Optimisation and scaling of interfacial GeO2 layers for high-k gate stacks on germanium and extraction of dielectric constant of GeO2

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. In this paper, GeO2 has been investigated as an interfacial layer for high-kappa gate stacks on germanium. Thermally grown GeO2 layers have been prepared at 550 degrees C to minimise GeO volatilisation. GeO2 growth has been performed in both pure O-2 ambient and O-2 diluted with N-2. GeO2 thickness has been scaled down to approximately 3 nm. MOS capacitors have been fabricated using different GeO2 thicknesses with a standard high-kappa dielectric on top. Electrical properties and thermal stability have been tested up to at least 350 degrees C. The K value of GeO2 was experimentally determined to be 4.5. Interface state densities (D-it) of less than 10(12) CM-2 eV(-1) have been extracted for all devices using the conductance method.

Understanding controls on cirque floor altitudes: insights from Kamchatka

Glacial cirques reflect former regions of glacier initiation, and are therefore used as indicators of past climate. One specific way in which palaeoclimatic information is obtained from cirques is by analysing their elevations, on the assumption that cirque floor altitudes are a proxy for climatically controlled equilibrium-line altitudes (ELAs) during former periods of small scale (cirque-type) glaciation. However, specific controls on cirque altitudes are rarely assessed, and the validity of using cirque floor altitudes as a source of palaeoclimatic information remains open to question. In order to address this, here we analyse the distribution of 3520 ice-free cirques on the Kamchatka Peninsula (eastern Russia), and assess various controls on their floor altitudes. In addition, we analyse controls on the mid-altitudes of 503 modern glaciers, currently identifiable on the peninsula, and make comparisons with the cirque altitude data. The main study findings are that cirque floor altitudes increase steeply inland from the Pacific, suggesting that moisture availability (i.e., proximity to the coastline) played a key role in regulating the altitudes at which former (cirque-forming) glaciers were able to initiate. Other factors, such as latitude, aspect, topography, geology and neo-tectonics seem to have played a limited (but not insignificant) role in regulating cirque floor altitudes, though south-facing cirques are typically higher than their north-facing equivalents, potentially reflecting the impact of prevailing wind directions (from the SSE) and/or variations in solar radiation on the altitudes at which former glaciers were able to initiate. Trends in glacier and cirque altitudes across the peninsula are typically comparable (i.e., values typically rise from both the north and south, inland from the Pacific coastline, and where glaciers/cirques are south-facing), yet the relationship with latitude is stronger for modern glaciers, and the relationship with distance to the coastline (and to a lesser degree with aspect) is notably weaker. These differences suggest that former glacier initiation (leading to cirque formation) was largely regulated by moisture availability (during winter months) and the control this exerted on accumulation; whilst the survival of modern glaciers is also strongly regulated by the variety of climatic and non climatic factors that control ablation. As a result, relationships between modern glacier mid-altitudes and peninsula-wide climatic trends are more difficult to identify than when cirque floor altitudes are considered (i.e., cirque-forming glaciers were likely in climatic equilibrium, whereas modern glaciers may not be).