L'Origine. Une lecture du poeme 'Radix, Matrix' de Paul Celan

This article presents a very close analysis of one poem by Paul Celan, demonstrating the important place of Jewish mysticism in his poetry and poetics.

Mixed radix Reed-Muller expansions

The choice of radix is crucial for multi-valued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multi-valued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesise logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to firstly estimate the potential of the new approach and to secondly analyse its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices.

High-radix systolic modular multiplication on reconfigurable hardware

The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

The pace of Holocene vegetation change - testing for synchronous developments

Mid to high latitude forest ecosystems have undergone several major compositional changes during the Holocene. The temporal and spatial patterns of these vegetation changes hold potential information to their causes and triggers. Here we test the hypothesis that the timing of vegetation change was synchronous on a sub-continental scale, which implies a common trigger or a step-like change in climate parameters. Pollen diagrams from selected European regions were statistically divided into assemblage zones and the temporal pattern of the zone boundaries analysed. The results show that the temporal pattern of vegetation change was significantly different from random. Times of change cluster around8.2, 4.8, 3.7, and 1.2 ka, while times of higher than average stability were found around 2.1 and 5.1 ka.Compositional changes linked to the expansion of Corylus avellana and Alnus glutinosa centre around 10.6 and 9.5 ka, respectively. A climatic trigger initiating these changes may have occurred 0.5 to 1 ka earlier, respectively. The synchronous expansion of C. avellana and A. glutinosa exemplify that dispersal is not necessarily followed by population expansion. The partly synchronous, partly random expansion of A. glutinosa in adjacent European regions exemplifies that sudden synchronous population expansions are not species specific traits but vary regionally.

A novel calmodulin-like protein from the liver fluke, Fasciola hepatica

An 18.2 kDa protein from the liver fluke, Fasciola hepatica has been identified and characterised. The protein shows strongest sequence similarity to egg antigen proteins from Schistosoma mansoni, Schistosoma japonicum and Clonorchis sinensis. The protein is predicted to adopt a calmodulin-like fold; it thus represents the third calmodulin-like protein to be characterised in F. hepatica and has been named FhCaM3. Compared to the classical calmodulin structure there are some variations. Most noticeably, the central, linker helix is disrupted by a cysteine residue. Alkaline native gel electrophoresis showed that FhCaM3 binds calcium ions. This binding event increases the ability of the protein to bind the hydrophobic fluorescent probe 8-anilinonaphthalene-1-sulphonate, consistent with an increase in surface hydrophobicity as seen in other calmodulins. FhCaM3 binds to the calmodulin antagonists trifluoperazine and W7, but not to the myosin regulatory light chain binding compound praziquantel. Immunolocalisation demonstrated that the protein is found in eggs and vitelline cells. Given the critical role of calcium ions in egg formation and hatching this suggests that FhCaM3 may play a role in calcium signalling in these processes. Consequently the antagonism of FhCaM3 may, potentially, offer a method for inhibiting egg production and thus reducing the spread of infection.

RNA interference targeting cathepsin B of the carcinogenic liver fluke, Opisthorchis viverrini

Functional genomics have not been reported for Opisthorchis viverrini or the related fish-borne fluke, Clonorchis sinensis. Here we describe the introduction by square wave electroporation of Cy3-labeled small RNA into adult O. viverrini worms. Adult flukes were subjected to square wave electroporation employing a single pulse for 20 ms of 125V in the presence of 50 µg/ml of Cy3-siRNA. The parasites tolerated this manipulation and, at 24 and 48 h after electroporation, fluorescence from the Cy3-siRNA was evident throughout the parenchyma of the worms, with strong fluorescence evident in the guts and reproductive organs of the adult worms. Second, other worms were treated using the same electroporation settings with double stranded RNA targeting an endogenous papain-like cysteine protease, cathepsin B. This manipulation resulted in a significant reduction in specific mRNA levels encoding cathepsin B, and a significant reduction in cathepsin B activity against the diagnostic peptide, Z-Arg-Arg-AMC. This appears to be the first report of introduction of reporter genes into O. viverrini and the first report of experimental RNA interference (RNAi) in this fluke. The findings indicated the presence of an intact RNAi pathway in these parasites which, in turn, provides an opportunity to probe gene functions in this neglected tropical disease pathogen.

SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described. © 1994 Kluwer Academic Publishers.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

New algorithms and VLSI architectures for SRT division and square root

In real time digital signal processing, high performance modules for division and square root are essential if many powerful algorithms are to be implemented. In this paper, a new radix 2 algorithms for SRT division and square root are developed. For these new schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures to implement the new division and square root schemes are also presented.

Constant scale factor, on-line CORDIC algorithm in the circular coordinate system

Real time digital signal processing requires the development of high performance arithmetic algorithms suitable for VLSI design. In this paper, a new online, circular coordinate system CORDIC algorithm is described, which has a constant scale factor. This algorithm was developed using a new Angular Representation (AR) model A radix 2 version of the CORDIC algorithm is presented, along with an architecture suitable for VLSI implementation.