Statistical Analysis of Wind Power Generation in Europe

Studies have shown that large geographical spreading can reduce the wind power variability and smooth production. It is frequently assumed that storage and interconnection can manage wind power variability and are totally flexible. However, constraints do exist. In the future more and more electricity will be provided by renewable energy sources and more electricity interconnectors will be built between European Union (EU) countries, as outlines in many of the Projects of Common Interests. It is essential to understand the correlation of wind generation throughout Europe considering power system constraints. In this study the spatial and temporal correlation of wind power production across several countries is examined in order to understand how “the wind ‘travels’ across Europe”. Three years of historical hourly wind power generation from ten EU countries is analysed to investigate the geographic diversity and time scales influence on correlation of wind power variations. Results are then compared with two other studies and show similar general characteristics of correlation between EU country pairs to identify opportunities for storage optimisation, power system operations, and trading.

Diagnostic based modeling for determining absolute atomic oxygen densities in atmospheric pressure helium-oxygen plasmas

Absolute atomic oxygen ground state densities in a radio-frequency driven atmospheric pressure plasma jet, operated in a helium-oxygen mixture, are determined using diagnostic based modeling. One-dimensional numerical simulations of the electron dynamics are combined with time integrated optical emission spectroscopy. The population dynamics of the upper O 3p 3P (l=844 nm) atomic oxygen state is governed by direct electron impact excitation, dissociative excitation, radiation losses, and collisional induced quenching. Absolute values for atomic oxygen densities are obtained through comparison with the upper Ar 2p1 (l=750.4 nm) state. Results for spatial profiles and power variations are presented and show excellent quantitative agreement with independent two-photon laser-induced fluorescence measurements.

A Theoretical and Experimental Study of Resonance in a High Performance Engine Intake System: Part 1

The unsteady gas dynamic phenomena in engine intake systems of the type found in racecars have been examined. In particular, the resonant tuning effects, including cylinder-to-cylinder power variations, which can occur as a result of the interaction between an engine and its airbox have been considered. Frequency analysis of the output from a Virtual 4-Stroke 1D engine simulation was used to characterise the forcing function applied by an engine to an airbox. A separate computational frequency sweeping technique, which employed the CFD package FLUENT, was used to determine the natural frequencies of virtual airboxes in isolation from an engine. Using this technique, an airbox with a natural frequency at 75 Hz was designed for a Yamaha R6 4-cylinder motorcycle engine. The existence of an airbox natural frequency at 75 Hz was subsequently confirmed by an experimental frequency sweeping technique carried out on the engine test bed. A coupled 1D/3D analysis which employed the engine simulation package Virtual 4-Stroke and the CFD package FLUENT, was used to model the combined engine and airbox system. The coupled 1D/3D analysis predicted a 75 Hz resonance of the airbox at an engine speed of 9000 rpm. This frequency was the induction frequency for a single cylinder. An airbox was fabricated and tested on the engine. Static pressure was recorded at a grid of points in the airbox as the engine was swept through a speed range of 3000 to 10000 rpm. The measured engine speed corresponding to resonance in the airbox agreed well with the predicted values. There was also good correlation between the amplitude and phase of the pressure traces recorded within the airbox and the 1D/3D predictions.

Robustness of Damping Control Implemented by Energy Storage Systems Installed in Power Systems

An energy storage system (ESS) installed in a power system can effectively damp power system oscillations through controlling exchange of either active or reactive power between the ESS and power system. This paper investigates the robustness of damping control implemented by the ESS to the variations of power system operating conditions. It proposes a new analytical method based on the well-known equal-area criterion and small-signal stability analysis. By using the proposed method, it is concluded in the paper that damping control implemented by the ESS through controlling its active power exchange with the power system is robust to the changes of power system operating conditions. While if the ESS damping control is realized by controlling its reactive power exchange with the power system, effectiveness of damping control changes with variations of power system operating condition. In the paper, an example power system installed with a battery ESS (BESS) is presented. Simulation results confirm the analytical conclusions made in the paper about the robustness of ESS damping control. Laboratory experiment of a physical power system installed with a 35kJ/7kW SMES (Superconducting Magnetic Energy Storage) was carried out to evaluate theoretical study. Results are given in the paper, which demonstrate that effectiveness of SMES damping control realized through regulating active power is robust to changes of load conditions of the physical power system.

Sensitivity characteristics of inverse Class-E power amplifier

In this paper, an analysis is performed in order to determine the effects that variations in circuit component values, frequency, and duty cycle have on the performance of the newly introduced inverse Class-E amplifier. Analysis of the inverse Class-E amplifier under the generalized condition of arbitrary duty cycle is performed and it is shown that the inverse Class-E amplifier is reasonably tolerant to circuit parameter variations. When compared to the conventional Class-E amplifier the inverse Class-E amplifier offers the potential for high efficiency at increased output power as well as higher peak output power levels than are available with a conventional Class-E amplifier. Further the inverse Class-E amplifier provides more flexibility for deployment with a pulsewidth modulator as the means of producing full-carrier amplitude modulation (AM) due to its ability to operate to high AM modulation indices.

SuperWASP observations of long timescale photometric variations in cataclysmic variables

Aims: We investigated whether the predictions and results of Stanishev et al. (2002, A&A, 394, 625) concerning a possible relationship between eclipse depths in PX And and its retrograde disc precession phase, could be confirmed in long term observations made by SuperWASP. In addition, two further CVs (DQ Her and V795 Her) in the same SuperWASP data set were investigated to see whether evidence of superhump periods and disc precession periods were present and what other, if any, long term periods could be detected. Methods: Long term photometry of PX And, V795 Her and DQ Her was carried out and Lomb-Scargle periodogram analysis undertaken on the resulting light curves. For the two eclipsing CVs, PX And and DQ Her, we analysed the potential variations in the depth of the eclipse with cycle number. Results: The results of our period and eclipse analysis on PX And confirm that the negative superhump period is 0.1417 ± 0.0001d. We find no evidence of positive superhumps in our data suggesting that PX And may have been in a low state during our observations. We improve on existing estimates of the disc precession period and find it to be 4.43 ± 0.05d. Our results confirm the predictions of Stanishev et al. (2002). We find that DQ Her does not appear to show a similar variation for we find no evidence of negative superhumps or of a retrograde disc precession. We also find no evidence of positive superhumps or of a prograde disc precession and we attribute the lack of positive superhumps in DQ Her to be due to the high mass ratio of this CV. We do however find evidence for a modulation of the eclipse depth over a period of 100 days which may be linked with solar-type magnetic cycles which give rise to long term photometric variations. The periodogram analysis for V795 Her detected the likely positive superhump period 0.1165d, however, neither the 0.10826d orbital period nor the prograde 1.53d disc precession period were seen. Here though we have found a variation in the periodogram power function at the positive superhump period, over a period of at least 120 days.

Improved Direct Power Control of Grid Connected DC/AC Converters

This paper proposes new direct power control (DPC) strategies for three-phase DC/AC converters with improved dynamic response and steady-state performance. As with an electrical machine, source and converter flux which equal the integration of the respective source and converter voltage are used to define active and reactive power flow. Optimization of the look-up-table used in conventional DPC is outlined first, to improve the power control and reduce the current distortion. Then constant switching frequency DPC is developed where the required converter voltage vector within a fixed half switching period is calculated directly from the active and reactive power errors. Detailed angle compensation due to the finite sampling frequency and the use of integral controller to further improve the power control accuracy, are described. Both simulation and experimental results are used to compare conventional DPC and vector control, and to demonstrate the effectiveness and robustness of the proposed control strategies during active and reactive power steps, and line inductance variations.

Determination of Power System Response during Small Load Fluctuations

This paper proposes a calculation method to determine power system response during small load perturbations or minor disturbances. The method establishes the initial value of active power transient using traditional reduction technique on admittance matrix, which incorporates voltage variations in the determination. The method examines active power distribution among generators when several loads simultaneously change, and verifies that the superposition principle is applicable for this scenario. The theoretical derivation provided in the paper is validated by numerical simulations using a 3-generator 9-bus benchmark model. The results indicate that the inclusion of voltage variation renders an independent and precise measure of active power response during transient conditions.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.