Error sensitive historical GIS: Identifying areal interpolation errors in time series data

Historical GIS has the potential to re-invigorate our use of statistics from historical censuses and related sources. In particular, areal interpolation can be used to create long-run time-series of spatially detailed data that will enable us to enhance significantly our understanding of geographical change over periods of a century or more. The difficulty with areal interpolation, however, is that the data that it generates are estimates which will inevitably contain some error. This paper describes a technique that allows the automated identification of possible errors at the level of the individual data values.

Interpolation formula between very low and intermediate-to-high damping Kramers escape rates for single-domain ferromagnetic particles

It is shown that the Mel'nikov-Meshkov formalism for bridging the very low damping (VLD) and intermediate-to-high damping (IHD) Kramers escape rates as a function of the dissipation parameter for mechanical particles may be extended to the rotational Brownian motion of magnetic dipole moments of single-domain ferromagnetic particles in nonaxially symmetric potentials of the magnetocrystalline anisotropy so that both regimes of damping, occur. The procedure is illustrated by considering the particular nonaxially symmetric problem of superparamagnetic particles possessing uniaxial anisotropy subject to an external uniform field applied at an angle to the easy axis of magnetization. Here the Mel'nikov-Meshkov treatment is found to be in good agreement with an exact calculation of the smallest eigenvalue of Brown's Fokker-Planck equation, provided the external field is large enough to ensure significant departure from axial symmetry, so that the VLD and IHD formulas for escape rates of magnetic dipoles for nonaxially symmetric potentials are valid.

Positive dilations of piecewise monotonic Markov maps

We provide an explicit formula which gives natural extensions of piecewise monotonic Markov maps defined on an interval of the real line. These maps are exact endomorphisms and define chaotic discrete dynamical systems.

Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

A bargaining set for monotonic simple games based on external and internal stability

A new bargaining set based on notions of both internal and external stability is developed in the context of endogenous coalition formation. It allows to make an explicit distinction between within-group and outside-group deviation options. This type of distinction is not present in current bargaining sets. For the class of monotonic proper simple games, the outcomes in the bargaining set are characterized. Furthermore, it is shown that the bargaining set of any homogeneous weighted majority game contains an outcome for which the underlying coalition structure consists of a minimal winning coalition and its complement.

Polynomial Functions and the Riesz Interpolation Property

Building on a proof by D. Handelman of a generalisation of an example due to L. Fuchs, we show that the space of real-valued polynomials on a non-empty set X of reals has the Riesz Interpolation Property if and only if X is bounded.

Multi-standard sub-pixel interpolation architecture for video motion estimation

A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video Motion Estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard. ©2008 IEEE.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.