Design, Manufacture and Performance of Germanium Bipolar Transistors

Germanium NPN bipolar transistors have been manufactured using phosphorus and boron ion implantation processes. Implantation and subsequent activation processes have been investigated for both dopants. Full activation of phosphorus implants has been achieved with RTA schedules at 535?C without significant junction diffusion. However, boron implant activation was limited and diffusion from a polysilicon source was not practical for base contact formation. Transistors with good output characteristics were achieved with an Early voltage of 55V and common emitter current gain of 30. Both Silvaco process and device simulation tools have been successfully adapted to model the Ge BJT(bipolar junction transistor) performance.

Differences in expression of junctional adhesion molecule-A and beta catenin in multiple sclerosis brain tissue: increasing evidence for the role of tight junction pathology

Previously we have employed antibodies to the tight junction (TJ)-associated proteins ZO-1 and occludin to describe endothelial tight junction abnormalities, in lesional and normal appearing white matter, in primary and secondary progressive multiple sclerosis (MS). This work is extended here by use of antibodies to the independent TJ-specific proteins and junctional adhesion molecule A & B (JAM-A, JAM-B). We have also assessed the expression in MS of ß-catenin, a protein specific to the TJ-associated adherens junction. Immunocytochemistry and semiquantitative confocal microscopy for JAM-A and ß-catenin was performed on snap-frozen sections from MS cases (n = 11) and controls (n = 6). Data on 1,443 blood vessels was acquired from active lesions (n = 13), inactive lesions (n = 13), NAWM (n = 20) and control white matter (n = 13). In MS abnormal JAM-A expression was found in active (46%) and inactive lesions (21%), comparable to previous data using ZO-1. However, a lower level of TJ abnormality was found in MS NAWM using JAM-A (3%) compared to ZO-1 (13%). JAM-B was strongly expressed on a small number of large blood vessels in control and MS tissues but at too low a level for quantitative analysis. By comparison with the high levels of abnormality observed with the TJ proteins, the adherens junction protein ß-catenin was normally expressed in all MS and control tissue categories. These results confirm, by use of the independent marker JAM-A, that TJ abnormalities are most frequent in active white matter lesions. Altered expression of JAM-A, in addition to affecting junctional tightness may also both reflect and affect leukocyte trafficking, with implications for immune status within the diseased CNS. Conversely, the adherens junction component of the TJ, as indicated by ß-catenin expression is normally expressed in all MS and control tissue categories.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.