From PASS 1 to YES to AND logic: building parallel processing into molecular logic gates by sequential addition of receptors

The synthesis and photophysical characterization of a novel molecular logic gate 4, operating in water, is demonstrated based on the competition between. fluorescence and photoinduced electron transfer (PET). It is constructed according to a 'fluorophore-spacer-receptor(1)-spacer-receptor(2)' format where anthracene is the. fluorophore, receptor(1) is a tertiary amine and receptor(2) is a phenyliminodiacetate ligand. Using only protons and zinc cations as the chemical inputs and. fluorescence as the output, 4 is demonstrated to be both a two-input AND and INH logic gate. When 4 is examined in context to the YES logic gates 1 and 2, and the two-input AND logic gate 3 and three-input AND logic gate 5, each with one or more of the following receptors including a tertiary amine, phenyliminodiacetate or benzo-15-crown-5 ether, logic gate 4 is the missing link in the homologous series. Collectively, the molecular logic gates 1-5 corroborate the PET 'fluorophore-spacer-receptor' model using chemical inputs and a light-signal output and provide insight into controlling the. fluorescence quantum yield of future PET-based molecular logic gates.

Apparatus and method for adjusting filter frequency in relation to sampling frequency

A self-tuning filter is disclosed. The self-tuning filter includes a digital clocking signal and an input coupled to the digital clocking signal, whereby the input reads a value incident on the input when the digital clocking signal changes to a predetermined state. A clock-tunable filter is, furthermore, coupled to the digital clocking signal so that the frequency of the clock-tunable filter is adjusted in relation to a sampling frequency at which the digital clocking signal operates. The self-tuning filter may be applied to an input of a data acquisition unit and applied to an input having a variable sampling frequency. A method of controlling the frequency of a clock-tunable filter is also disclosed.

Detection of Entanglement in Ultracold Lattice Gases

Probing non trivial magnetic ordering in quantum magnets realized with ultracold lattice gases demands detection methods with some spatial resolution built on it. Here we demonstrate that the Faraday matter-light interface provides an experimentally feasible tool to distinguish indubitably different quantum phases of a given many-body system in a non-demolishing way. We illustrate our approach by focussing on the Heisenberg chain for spin-1 bosons in the presence of a SU(2) symmetry breaking field. We explain how using the light signal obtained via homodyne detection one can reconstruct the phase diagram of the model. Further we show that the very same technique that provides a direct experimentally measurable signal of different order parameters can be extended to detect also the presence of multipartite entanglement in such systems.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Concordance between digital pathology and light microscopy in general surgical pathology: A pilot study of 100 cases

Aim (1)
A pilot study to determine the accuracy of interpretation of whole slide digital images in a broad range of general histopathology cases of graded complexity. (2) To survey the participating histopathologists with regard to acceptability of digital pathology.

Materials and methods
Glass slides of 100 biopsies and minor resections were digitally scanned in their entirety, producing digital slides. These cases had been diagnosed by light microscopy at least 1 year previously and were subsequently reassessed by the original reporting pathologist (who was blinded to their original diagnosis) using digital pathology. The digital pathology-based diagnosis was compared with the original glass slide diagnosis and classified as concordant, slightly discordant (without clinical consequence) or discordant. The participants were surveyed at the end of the study.

Results
There was concordance between the original light microscopy diagnosis and digital pathology-based diagnosis in 95 of the 100 cases while the remaining 5 cases showed only slight discordance (with no clinical consequence). None of the cases were categorised as discordant. Participants had mixed experiences using digital pathology technology.

Conclusions
In the broad range of cases we examined, digital pathology is a safe and viable method of making a primary histopathological diagnosis.

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.

Digital Baseband Predistortion Based Linearized Broadband Inverse Class-E Power Amplifier

A newly introduced inverse class-E power amplifier (PA) was designed, simulated, fabricated, and characterized. The PA operated at 2.26 GHz and delivered 20.4-dBm output power with peak drain efficiency (DE) of 65% and power gain of 12 dB. Broadband performance was achieved across a 300-Mitz bandwidth with DE of better than 50% and 1-dB output-power flatness. The concept of enhanced injection predistortion with a capability to selectively suppress unwanted sub-frequency components and hence suitable for memory effects minimization is described coupled with a new technique that facilitates an accurate measurement of the phase of the third-order intermodulation (IM3) products. A robust iterative computational algorithm proposed in this paper dispenses with the need for manual tuning of amplitude and phase of the IM3 injected signals as commonly employed in the previous publications. The constructed inverse class-E PA was subjected to a nonconstant envelope 16 quadrature amplitude modulation signal and was linearized using combined lookup table (LUT) and enhanced injection technique from which superior properties from each technique can be simultaneously adopted. The proposed method resulted in 0.7% measured error vector magnitude (in rms) and 34-dB adjacent channel leakage power ratio improvement, which was 10 dB better than that achieved using the LUT predistortion alone.

Parametric FIR Design of Propagation Loss Filters in Digital Waveguide String Models

One of the attractive features of sound synthesis by physical modeling is the potential to build acoustic-sounding digital instruments that offer more flexibility and different options in its design and control than their real-life counterparts. In order to develop such virtual-acoustic instruments, the models they are based on need to be fully parametric, i.e., all coefficients employed in the model are functions of physical parameters that are controlled either online or at the (offline) design stage. In this letter we show how propagation losses can be parametrically incorporated in digital waveguide string models with the use of zero-phase FIR filters. Starting from the simplest possible design in the form of a three-tap FIR filter, a higher-order FIR strategy is presented and discussed within the perspective of string sound synthesis with digital waveguide models.

DESIGNING VLSI SIGNAL PROCESSING CHIPS USING DATA DEPENDENCE GRAPHS.

The highly structured nature of many digital signal processing operations allows these to be directly implemented as regular VLSI circuits. This feature has been successfully exploited in the design of a number of commercial chips, some examples of which are described. While many of the architectures on which such chips are based were originally derived on heuristic basis, there is an increasing interest in the development of systematic design techniques for the direct mapping of computations onto regular VLSI arrays. The purpose of this paper is to show how the the technique proposed by Kung can be readily extended to the design of VLSI signal processing chips where the organisation of computations at the level of individual data bits is of paramount importance. The technique in question allows architectures to be derived using the projection and retiming of data dependence graphs.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

VLSI architectures for digital image coding

A number of high-performance VLSI architectures for real-time image coding applications are described. In particular, attention is focused on circuits for computing the 2-D DCT (discrete cosine transform) and for 2-D vector quantization. The former circuits are based on Winograd algorithms and comprise a number of bit-level systolic arrays with a bit-serial, word-parallel input. The latter circuits exhibit a similar data organization and consist of a number of inner product array circuits. Both circuits are highly regular and allow extremely high data rates to be achieved through extensive use of parallelism.