The effects of TMS over dorsolateral prefrontal cortex on trans-saccadic memory of multiple objects

Humans typically make several rapid eye movements (saccades) per second. It is thought that visual working memory can retain and spatially integrate three to four objects or features across each saccade but little is known about this neural mechanism. Previously we showed that transcranial magnetic stimulation (TMS) to the posterior parietal cortex and frontal eye fields degrade trans-saccadic memory of multiple object features (Prime, Vesia, & Crawford, 2008, Journal of Neuroscience, 28(27), 6938-6949; Prime, Vesia, & Crawford, 2010, Cerebral Cortex, 20(4), 759-772.). Here, we used a similar protocol to investigate whether dorsolateral prefrontal cortex (DLPFC), an area involved in spatial working memory, is also involved in trans-saccadic memory. Subjects were required to report changes in stimulus orientation with (saccade task) or without (fixation task) an eye movement in the intervening memory interval. We applied single-pulse TMS to left and right DLPFC during the memory delay, timed at three intervals to arrive approximately 100ms before, 100ms after, or at saccade onset. In the fixation task, left DLPFC TMS produced inconsistent results, whereas right DLPFC TMS disrupted performance at all three intervals (significantly for presaccadic TMS). In contrast, in the saccade task, TMS consistently facilitated performance (significantly for left DLPFC/perisaccadic TMS and right DLPFC/postsaccadic TMS) suggesting a dis-inhibition of trans-saccadic processing. These results are consistent with a neural circuit of trans-saccadic memory that overlaps and interacts with, but is partially separate from the circuit for visual working memory during sustained fixation.

Marketing secondhand goods in late medieval England

Purpose – The purpose of this paper is to identify the main practitioners, goods, customers and locations of secondhand marketing activities in late medieval England. It questions how important was the economic role played by such markets and what was the interaction with more formal market structures?

Design/methodology/approach – A broad range of evidence was examined, covering the period from 1200 to 1500: regulations, court rolls, wills, manorial accounts, literature, and even archaeology. Such material often provided mere scraps of information about marginal marketing activity and it was important to recognise the severe limitations of the evidence. Nevertheless, a wide survey of the available sources can give us an insight into medieval attitudes towards such trade, as well as reminding us that much marketing activity occurred beyond the reach of the surviving documentation.

Findings – Late medieval England had numerous outlets for secondhand items, from sellers of used clothes and furs who wandered the marketplaces to craftsmen who recycled and mended old materials. Secondhand marketing was an important part of the medieval makeshift economy, serving not only the needs of the lower sectors of society but also those aspiring to a higher status. However, it is unlikely that such trade generated much profit and the traders were often viewed as marginal, suspicious and even fraudulent.

Originality/value – There is a distinct lack of research into the extent of and significance of medieval secondhand marketing, which existed in the shadowy margins of formal markets and is thus poorly represented in the primary sources. A broad-based approach to the evidence can highlight a variety of important issues, which impact upon the understanding of the medieval English economy.

‘Reading Aran knitting: stitches, text andinterpretation’

The densely textured surfaces of Aran knitting seem to invite interpretation. They have been ‘read’ as identity documents, family trees, references to natural and spiritual phenomena, or even maps. This paper traces the search for meaning in Aran knitting, examining how these stitch patterns have been ‘read’ in the contexts of tourism, fine art and fashion. As Jo Turney (2013:55) argues, the idea of knitted textiles as communicative media in non-literate societies ‘consigns the garments to a preindustrial era of more rural and simple times’, situating them in an imagined state of ‘stasis’. Thus the ways in which Aran stitches are ‘read’ sometimes obscure the processes through which they are ‘written’, whether in terms of individual authorship and creativity, or in terms of their manufacture. Regardless of the historical veracity of claims that particular Aran stitch patterns index features of the social, natural or spiritual worlds, analysing the ways they have been ‘read’ in the context of comparable textile traditions, other crafts which have taken on ‘heritage’ souvenir status, and Irish national identity, reveals how Aran knitting has performed broader communicative functions (see Sonja Andrew 2008), which continue to be subverted and elaborated by fine artists, and translated into couture and mass market fashion products.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Control of leaky-mode propagation and radiation properties in hybrid dielectric-waveguide printed-circuit technology: Experimental results

Experimental results are presented to show how a planar circuit, printed on a laterally shielded dielectric waveguide, can induce and control the radiation from a leaky-mode. By studying the leaky-mode complex propagation constant, a desired radiation pattern can be synthesized, controlling the main radiation characteristics (pointing direction, beamwidth, sidelobes level) for a given frequency, This technique leads to very flexible and original leaky-wave antenna designs. The experiments show to be in very good agreement with the leaky-mode theory.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

Implementation of a network flow lookup circuit for next-generation packet classifiers

This paper presents a lookup circuit with advanced memory techniques and algorithms that examines network packet headers at high throughput rates. Hardware solutions and test scenarios are introduced to evaluate the proposed approach. The experimental results show that the proposed lookup circuit is able to achieve at least 39 million packet header lookups per second, which facilitates the application of next-generation stateful packet classifications at beyond 20Gbps internet traffic throughput rates.

Design and analysis of matching circuit architectures for a closest match lookup

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. © 2006 IEEE.