High-frequency oscillations in a solar active region observed with the RAPID DUAL IMAGER

High-cadence, synchronized, multiwavelength optical observations of a solar active region (NOAA 10794) are presented. The data were obtained with the Dunn Solar Telescope at the National Solar Observatory/Sacramento Peak using a newly developed camera system: the rapid dual imager. Wavelet analysis is undertaken to search for intensity related oscillatory signatures, and periodicities ranging from 20 to 370 s are found with significance levels exceeding 95%. Observations in the H-α blue wing show more penumbral oscillatory phenomena when compared to simultaneous G-band observations. The H-α oscillations are interpreted as the signatures of plasma motions with a mean velocity of 20 km s-1. The strong oscillatory power over H-α blue-wing and G-band penumbral bright grains is an indication of the Evershed flow with frequencies higher than previously reported.

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. in order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small-signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y-parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S-22 in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright (C) 2006 John Wiley & Sons, Ltd.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.

CMOS compatible RF MEMS switches with serpentine springs

This paper describes a serpentine flexure spring design and fabrication process development for radio frequency microelectromechanical (RF MEMS) capacitive switches with coplanar waveguide (CPW) lines. Sputtered tungsten is employed as the CPW line conductor instead of Au, a non-Si compatible material. The bridge membrane is fabricated from Al. The materials and fabrication process can be integrated with CMOS and SOI technology to reduce cost. Results show the MEMS switch has excellent performance with insertion loss 0.3dB, return loss -27dB at 30GHz and high isolation -30dB at 40GHz. The process developed promises to simplify the design and fabrication of RF MEMS on silicon.

Evaluation of a Passive Millimeter Wave (PMMW) imager for wire detection in degraded visual conditions

Ground vehicle tests have been performed to evaluate the performance of a Passive Millimeter Wave (PMMW) imager in reduced visibility conditions and in particular, the ability to detect power lines and cables. A PMMW imager was
compared with Long Wave Infrared (LWIR) and visible imaging cameras. The three sensors were mounted on a Land Rover, together with GPS and digital recording system. All three sensors plus the GPS data were recorded simultaneously in order to provide direct comparisons. The vehicle collected imagery from a number of sites in the vicinity of Malvern, UK, in January, 2008. Imagery was collected both while the vehicle was stationary at specific sites
and while it was moving. Weather conditions during the data collection included clear, drizzle, rain and fog. Imagery was collected during the day, at night, and during dusk/dawn transition periods. The PMMW imager was a prototype which operated at 94 GHz and was based on a conically scanned folded Schmidt camera and the LWIR and visible sensors were commercial off the shelf items.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Ferroelectric hafnium oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories

With the ability to engineer ferroelectricity in HfO2 thin films, manufacturable and highly scaled MFM capacitors and MFIS-FETs can be implemented into a CMOS-environment. NVM properties of the resulting devices are discussed and contrasted to existing perovskite based FRAM.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.