Infrastructure and the Architectures of Modernity in Ireland 1916-2016

At the formation of the new Republic of Ireland, the construction of new infrastructures was seen as an essential element in the building of the new nation, just as the adoption of international style modernism in architecture was perceived as a way to escape the colonial past. Accordingly, infrastructure became the physical manifestation, the concrete identity of these objectives and architecture formed an integral part of this narrative. Moving between scales and from artefact to context, Infrastructure and the Architectures of Modernity in Ireland 1916-2016 provides critical insights and narratives on what is a complex and hitherto overlooked landscape, one which is often as much international as it is Irish. In doing so, it explores the interaction between the universalising and globalising tendencies of modernisation on one hand and the textures of local architectures on the other.

The book shows how the nature of technology and infrastructure is inherently cosmopolitan. Beginning with the building of the heroic Shannon hydro-electric facility at Ardnacrusha by the German firm of Siemens-Schuckert in the first decade of independence, Ireland became a point of varying types of intersection between imported international expertise and local need. Meanwhile, at the other end of the century, by the year 2000, Ireland had become one of the most globalized countries in the world, site of the European headquarters of multinationals such as Google and Microsoft. Climatically and economically expedient to the storing and harvesting of data, Ireland has subsequently become a repository of digital information farmed in large, single-storey sheds absorbed into anonymous suburbs. In 2013, it became the preferred site for Intel to design and develop its new microprocessor chip: the Galileo. The story of the decades in between, of shifts made manifest in architecture and infrastructure from the policies of economic protectionism, to the opening up of the country to direct foreign investment and the embracing of the EU, is one of the influx of technologies and cultural references into a small country on the edges of Europe as Ireland became both a launch-pad and testing ground for a series of aspects of designed modernity.

Infra-Éireann: Making Ireland Modern - Irish Pavilion for the 14th Architectural biennale, Venice 2014.

After an open competition, we were selected to commission, curate and design the Irish pavilion for the Venice biennale 2014. Our proposal engage with the role of infrastructure and architecture in the cultural development of the new Irish state 1914-2014. This curatorial programme was realised in a demountable, open matrix pavilion measuring 12 x 5 x 6 metres.

How modernity is absorbed into national cultures usually presupposes an attachment to previous conditions and a desire to reconcile the two. In an Irish context, due to the processes of de-colonisation and political independence, this relationship is more complicated.

In 1914, Ireland was largely agricultural and lacked any significant industrial complex. The construction of new infrastructures after independence in 1921 became central to the cultural imagining of the new nation. The adoption of modernist architecture was perceived as a way to escape the colonial past. As the desire to reconcile cultural and technological aims developed, these infrastructures became both the physical manifestation and concrete identity of the new nation with architecture an essential element in this construct.

Technology and infrastructure are inherently cosmopolitan. Beginning with the Shannon hydro-electric facility at Ardnacrusha (1929) involving the German firm of Siemens-Schuckert, Ireland became a point of various intersections between imported international expertise and local need. By the turn of the last century, it had become one of the most globalised countries in the world, site of the European headquarters of multinationals such as Google and Microsoft. Climatically and economically expedient to the storing and harvesting of data, Ireland has subsequently become an important repository of digital information farmed in large, single-storey sheds absorbed into dispersed suburbs. In 2013, it became the preferred site for Intel to design and develop its new microprocessor board, the Galileo, a building block for the internet of things.

The story of the decades in between, of shifts made manifest in architecture and infrastructure, from the policies of economic protectionism to the embracing of the EU is one of the influx of technologies and cultural references into a small country on the edges of Europe: Ireland as both a launch-pad and testing ground for a series of aspects of designed modernity.

Accelerating integer-based fully homomorphic encryption using Comba multiplication

Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.

Efficiently Scheduling Task Dataflow Parallelism: A Comparison Between Swan and QUARK

Increased system variability and irregularity of parallelism in applications put increasing demands on the ef- ficiency of dynamic task schedulers. This paper presents a new design for a work-stealing scheduler supporting both Cilk- style recursively parallel code and parallelism deduced from dataflow dependences. Initial evaluation on a set of linear algebra kernels demonstrates that our scheduler outperforms PLASMA’s QUARK scheduler by up to 12% on a 16-thread Intel Xeon and by up to 50% on a 32-thread AMD Bulldozer.

Methods and Metrics for Fair Server Assessment under Real-Time Financial Workloads

We present a rigorous methodology and new metrics for fair comparison of server and microserver platforms. Deploying our methodology and metrics, we compare a microserver with ARM cores against two servers with ×86 cores running the same real-time financial analytics workload. We define workload-specific but platform-independent performance metrics for platform comparison, targeting both datacenter operators and end users. Our methodology establishes that a server based on the Xeon Phi co-processor delivers the highest performance and energy efficiency. However, by scaling out energy-efficient microservers, we achieve competitive or better energy efficiency than a power-equivalent server with two Sandy Bridge sockets, despite the microserver's slower cores. Using a new iso-QoS metric, we find that the ARM microserver scales enough to meet market throughput demand, that is, a 100% QoS in terms of timely option pricing, with as little as 55% of the energy consumed by the Sandy Bridge server.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

ALEA: Fine-Grain Energy Profiling with Basic Block Sampling

Energy efficiency is an essential requirement for all contemporary computing systems. We thus need tools to measure the energy consumption of computing systems and to understand how workloads affect it. Significant recent research effort has targeted direct power measurements on production computing systems using on-board sensors or external instruments. These direct methods have in turn guided studies of software techniques to reduce energy consumption via workload allocation and scaling. Unfortunately, direct energy measurements are hampered by the low power sampling frequency of power sensors. The coarse granularity of power sensing limits our understanding of how power is allocated in systems and our ability to optimize energy efficiency via workload allocation.
We present ALEA, a tool to measure power and energy consumption at the granularity of basic blocks, using a probabilistic approach. ALEA provides fine-grained energy profiling via sta- tistical sampling, which overcomes the limitations of power sens- ing instruments. Compared to state-of-the-art energy measurement tools, ALEA provides finer granularity without sacrificing accuracy. ALEA achieves low overhead energy measurements with mean error rates between 1.4% and 3.5% in 14 sequential and paral- lel benchmarks tested on both Intel and ARM platforms. The sampling method caps execution time overhead at approximately 1%. ALEA is thus suitable for online energy monitoring and optimization. Finally, ALEA is a user-space tool with a portable, machine-independent sampling method. We demonstrate two use cases of ALEA, where we reduce the energy consumption of a k-means computational kernel by 37% and an ocean modelling code by 33%, compared to high-performance execution baselines, by varying the power optimization strategy between basic blocks.