'Changing attitudes with a little imagination': Imagined contact effects on young children's intergroup bias

The current research tested a recent development in social psychology, namely 'imagined contact', among young children (n = 123, 5 to 10 years). Children imagined interacting with a physically disabled child, or did not take part in this activity (the control group). Compared with the control group, children who engaged in 'imagined contact' subsequently showed reduced intergroup bias in their general attitude and ratings of warmth and competence. Imagined contact also led to more positive intended friendship behavior towards the disabled, but only among 5 – 6 year olds. This provides partial support for our hypothesis that younger children, perhaps as a result of their lack of outgroup experience, are more likely to benefit from imagined contact. Implications for the development of attitudes towards the disabled, imagined contact theory and the development of classroom-based prejudice-reduction techniques based on imagined contact are discussed.

Accurate and Efficient Modelling to Calculate the Voltage Dependence of Liquid Crystal Based Reflectarray Cells

Two models that can predict the voltage-dependent scattering from liquid crystal (LC)-based reflectarray cells are presented. The validity of both numerical techniques is demonstrated using measured results in the frequency range 94-110 GHz. The most rigorous approach models, for each voltage, the inhomogeneous and anisotropic permittivity of the LC as a stratified media in the direction of the biasing field. This accounts for the different tilt angles of the LC molecules inside the cell calculated from the solution of the elastic problem. The other model is based on an effective homogeneous permittivity tensor that corresponds to the average tilt angle along the longitudinal direction for each biasing voltage. In this model, convergence problems associated with the longitudinal inhomogeneity are avoided, and the computation efficiency is improved. Both models provide a correspondence between the reflection coefficient (losses and phase-shift) of the LC-based reflectarray cell and the value of biasing voltage, which can be used to design beam scanning reflectarrays. The accuracy and the efficiency of both models are also analyzed and discussed.

Effect of magnetic bias on Gaussian pulse scattering by stacked nonlinear semiconductor layers

The nonlinear scattering of pulses by periodic stacks of semiconductor layers with magnetic bias has been studied in the self-consistent problem formulation, taking into account mobility of carriers. The three-wave mixing technique has been applied to the analysis of the waveform evolution in the stacks illuminated by two Gaussian pulses with different central frequencies and lengths. The effects of external magnetic bias, and stack physical and geometrical parameters on the properties of the scattered waveforms are discussed. © 2013 IEEE.

Sequential injection of domain walls into ferroelectrics at different bias voltages: Paving the way for “domain wall memristors”

Simple meso-scale capacitor structures have been made by incorporating thin (300 nm) single crystal lamellae of KTiOPO4 (KTP) between two coplanar Pt electrodes. The influence that either patterned protrusions in the electrodes or focused ion beam milled holes in the KTP have on the nucleation of reverse domains during switching was mapped using piezoresponse force microscopy imaging. The objective was to assess whether or not variations in the magnitude of field enhancement at localised “hot-spots,” caused by such patterning, could be used to both control the exact locations and bias voltages at which nucleation events occurred. It was found that both the patterning of electrodes and the milling of various hole geometries into the KTP could allow controlled sequential injection of domain wall pairs at different bias voltages; this capability could have implications for the design and operation of domain wall electronic devices, such as memristors, in the future.

Distribution Network Voltage Support Using Sensitivity-based Dispatch of Distributed Generation

This paper is concerned with the voltage and reactive power issues surrounding the connection of Distributed Generation (DG) on the low-voltage (LV) distribution network. The presented system-wide voltage control algorithm consists of three stages. Firstly available reactive power reserves are utilized. Then, if required, DG active power output is curtailed. Finally, curtailment of non-critical site demand is considered. The control methodology is tested on a variant of the 13-bus IEEE Node Radial Distribution Test Feeder. The presented control algorithm demonstrated that the distribution system operator (DSO) can maintain voltage levels within a desired statutory range by dispatching reactive power from DG or network devices. The practical application of the control strategy is discussed.

Bias in research

The aim of this article is to outline types of ‘bias’ across research designs, and consider strategies to minimise bias. Evidence-based nursing, defined as the “process by which evidence, nursing theory, and clinical expertise are critically evaluated and considered, in conjunction with patient involvement, to provide the delivery of optimum nursing care,”1 is central to the continued development of the nursing professional. Implementing evidence into practice requires nurses to critically evaluate research, in particular assessing the rigour in which methods were undertaken and factors that may have biased findings.

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration system level interactions and ensuring that under any change of operating conditions only the "lesscrucial" computations, that contribute less to block/system output quality, are affected. The design methodology applied to a DCT/IDCT system shows large power benefits (up to 69%) at reasonable image quality while tolerating errors induced by varying operating conditions (VOS, process variations, channel noise). Interestingly, the proposed IDCT scheme conceals channel noise at scaled voltages. ©2009 IEEE.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator

In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Spatially-resolved mapping of history-dependent coupled electrochemical and electronical behaviors of electroresistive NiO

Bias-induced oxygen ion dynamics underpins a broad spectrum of electroresistive and memristive phenomena in oxide materials. Although widely studied by device-level and local voltage-current spectroscopies, the relationship between electroresistive phenomena, local electrochemical behaviors, and microstructures remains elusive. Here, the interplay between history-dependent electronic transport and electrochemical phenomena in a NiO single crystalline thin film with a number of well-defined defect types is explored on the nanometer scale using an atomic force microscopy-based technique. A variety of electrochemically-active regions were observed and spatially resolved relationship between the electronic and electrochemical phenomena was revealed. The regions with pronounced electroresistive activity were further correlated with defects identified by scanning transmission electron microscopy. Using fully coupled mechanical-electrochemical modeling, we illustrate that the spatial distribution of strain plays an important role in electrochemical and electroresistive phenomena. These studies illustrate an approach for simultaneous mapping of the electronic and ionic transport on a single defective structure level such as dislocations or interfaces, and pave the way for creating libraries of defect-specific electrochemical responses.