Genomewide linkage scan of schizophrenia in a large multicenter pedigree sample using single nucleotide polymorphisms

A genomewide linkage scan was carried out in eight clinical samples of informative schizophrenia families. After all quality control checks, the analysis of 707 European-ancestry families included 1615 affected and 1602 unaffected genotyped individuals, and the analysis of all 807 families included 1900 affected and 1839 unaffected individuals. Multipoint linkage analysis with correction for marker-marker linkage disequilibrium was carried out with 5861 single nucleotide polymorphisms (SNPs; Illumina version 4.0 linkage map). Suggestive evidence for linkage ( European families) was observed on chromosomes 8p21, 8q24.1, 9q34 and 12q24.1 in nonparametric and/or parametric analyses. In a logistic regression allele-sharing analysis of linkage allowing for intersite heterogeneity, genomewide significant evidence for linkage was observed on chromosome 10p12. Significant heterogeneity was also observed on chromosome 22q11.1. Evidence for linkage across family sets and analyses was most consistent on chromosome 8p21, with a one-LOD support interval that does not include the candidate gene NRG1, suggesting that one or more other susceptibility loci might exist in the region. In this era of genomewide association and deep resequencing studies, consensus linkage regions deserve continued attention, given that linkage signals can be produced by many types of genomic variation, including any combination of multiple common or rare SNPs or copy number variants in a region. Molecular Psychiatry (2009) 14, 786-795; doi:10.1038/mp.2009.11; published online 17 February 2009

Investigation of swelling and network parameters of poly(ethylene glycol)-crosslinked poly(methyl vinyl ether-co-maleic acid) hydrogels

The influence of poly(ethylene glycol) (PEG) plasticiser content and molecular weight on the physicochemical properties of films cast from aqueous blends of poly(methyl vinyl ether-co-maleic acid) was investigated using thermal analysis, swelling studies, scanning electron microscopy (SEM) and attenuated total reflectance (ATR)-Fourier transform infrared (FTIR) spectroscopy. FTIR spectroscopy revealed a shift of the C{double bond, long}O peak from 1708 to 1731 cm, indicating that an esterification reaction had occurred upon heating, thus producing crosslinked films. Higher molecular weight PEGs (10,000 and 1000 Da, respectively), having greater chain length, producing hydrogel networks with lower crosslink densities and higher average molecular weight between two consecutive crosslinks. Accordingly, such materials exhibited higher swelling rates. Hydrogels crosslinked with a low molecular weight PEG (PEG 200) showed rigid networks with high crosslink densities and, therefore, lower swelling rates. Polymer:plasticizer ratio alteration did not yield any discernable patterns, regardless of the method of analysis. The polymer-water interaction parameter (?) increased with increases in the crosslink density. SEM studies showed that porosity of the crosslinked films increased with increasing PEG MW, confirming what had been observed with swelling studies and thermal analysis, that the crosslink density must be decreased as the M of the crosslinker is increased. Hydrogels containing PMVE/MA/PEG 10,000 could be used for rapid delivery of drug, due to their low crosslink density. Moderately crosslinked PMVE/MA/PEG 1000 hydrogels or highly crosslinked PMVE/MA/PEG 200 systems could then be used in controlling the drug delivery rates. We are currently evaluating these systems, both alone and in combination, for use in sustained release drug delivery devices. © 2008 Elsevier Ltd. All rights reserved.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

JPEG encoder system-on-a-chip demonstrator

The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.

Differential power analysis resistance of Camellia and countermeasure strategy on FPGAs

Security devices are vulnerable to Differential Power Analysis (DPA) that reveals the key by monitoring the power consumption of the circuits. In this paper, we present the first DPA attack against an FPGA implementation of the Camellia encryption algorithm with all key sizes and evaluate the DPA resistance of the algorithm. The Camellia cryptographic algorithm involves several different key-dependent intermediate operations including S-Box operations. In previous research, it was believed that the Camellia is stronger than AES due to the additional Whitening phase protecting the S-Box operation. However, we propose an attack that bypasses the Whitening phase and targets the S-Box. In this paper, we also discuss a lowcost countermeasure strategy to protect the Pre-whitening / Post-whitening and FL function of Camellia using Dual-rail Precharged Logic and to protect against attacks of the S-Box using Random Delay Insertion. © 2009 IEEE.

Parameterizable QR core

The design of a generic QR core for adaptive beamforming is presented. The work relies on an existing mapping technique that can be applied to a triangular QR array in such a way to allow the generation of a range of QR architectures. All scheduling of data inputs and retiming to include processor latency has been included within the generic representation.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Optimization of Weighted Finite State Transducer for Speech Recognition

There is considerable interest in creating embedded, speech recognition hardware using the weighted finite state transducer (WFST) technique but there are performance and memory usage challenges. Two system optimization techniques are presented to address this; one approach improves token propagation by removing the WFST epsilon input arcs; another one-pass, adaptive pruning algorithm gives a dramatic reduction in active nodes to be computed. Results for memory and bandwidth are given for a 5,000 word vocabulary giving a better practical performance than conventional WFST; this is then exploited in an adaptive pruning algorithm that reduces the active nodes from 30,000 down to 4,000 with only a 2 percent sacrifice in speech recognition accuracy; these optimizations lead to a more simplified design with deterministic performance.

Autonomic management of non-functional concerns in distributed & parallel application programming

An approach to the management of non-functional concerns in massively parallel and/or distributed architectures that marries parallel programming patterns with autonomic computing is presented. The necessity and suitability of the adoption of autonomic techniques are evidenced. Issues arising in the implementation of autonomic managers taking care of multiple concerns and of coordination among hierarchies of such autonomic managers are discussed. Experimental results are presented that demonstrate the feasibility of the approach.