Laser annealing of sputtered silicon for wafer-bonding applications

Sputtered silicon is investigated as a bonding layer for transfer of pre-processed silicon layers to various insulating substrates. Although the material appears suitable for low temperature processing, previous work has shown that gas trapped in the pores of the sputtered material is released at temperatures above 350 degrees C and further increases of temperature lead to destruction of any bonded interface. Pre-annealing at 1000 degrees C before bonding drives out gas and/or seals the surface, but for device applications where processing temperatures must be kept below about 300 degrees C, this technique cannot be used. In the current work, we have investigated the effect of excimer laser-annealing to heat the sputtered silicon surface to high temperature whilst minimising heating of the underlying substrate. Temperature profile simulations are presented and the results of RBS, TEM and AFM used to characterise the annealed layers. The results verify that gases are present in the sub-surface layers and suggest that while sealing of the surface is important for suppression of the out-diffusion of gases, immediate surface gas removal may also play a role. The laser-annealing technique appears to be an effective method of treating sputtered silicon, yielding a low roughness surface suitable for wafer bonding, thermal splitting and layer transfer.

Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Nanoscale ferroelectrics machined from single crystals

This paper summarises some of the most recent work that has been done on nanoscale ferroelectrics as a result of a joint collaborative research effort involving groups in Queen's University Belfast, the University of Cambridge and the University of St. Andrews. Attempts have been made to observe fundamental effects of reduced size, and increasing morphological complexity, on ferroelectric behaviour by studying the functional response and domain characteristics in nanoscale single crystal material, whose size and morphology have been defined by Focused Ion Beam (FIB) patterning. This approach to nanoshape fabrication has allowed the following broad statements to be made: (i) in single crystal BaTiO3 sheets, permittivity and phase transition behaviour is not altered from that of bulk material down to a thickness of similar to 75 nm; (ii) in single crystal BaTiO3 sheets and nanowires changes in observed domain morphologies are consistent with large scale continuum modeling.

Characteristics of the interfacial capacitance in thin film Ba0.5Sr0.5TiO3 capacitors with SrRuO3 and (La, Sr)CoO3 bottom electrodes

Thin film Ba0.5Sr0.5TiO3 (BST) capacitors of thickness similar to75 nm to similar to1200 nm, with Au top electrodes and SrRuO 3 (SRO) or (La, Sr)CoO3 (LSCO) bottom electrodes were fabricated using Pulsed Laser Deposition. Implementing the "series capacitor model," bulk and interfacial capacitance properties were extracted as a function of temperature and frequency. 'Bulk' properties demonstrated typical ceramic behaviour, displaying little frequency dependence and a permittivity and loss peak at 250 K and 150 K respectively. The interfacial component was found to be relatively temperature and frequency independent for the LSCO/BST capacitors, but for the SRO/BST configuration the interfacial capacitance demonstrated moderate frequency and little temperature dependence below T similar to 300 K but a relatively strong frequency and temperature dependence above T similar to3 00 K. This was attributed to the thermal activation of a space charge component combined with a thermally independent background. The activation energy for the space charge was found to be E-A similar to 0.6 eV suggesting de-trapping of electrons from shallow level traps associated with a thin interfacial layer of oxygen vacancies, parallel to the electrodes.

Thin film capacitor cut from single crystals using focused ion beam milling

The focused ion beam microscope (FIB) has been used to fabricate thin parallel-sided ferroelectric capacitors from single crystals of BaTiO3 and SrTiO3. A series of nano-sized capacitors ranging in thickness from similar to660 nm to similar to300 nm were made. Cross-sectional high resolution transmission electron microscopy (HRTEM) revealed that during capacitor fabrication, the FIB rendered around 20 nm of dielectric at the electrode-dielectric interface amorphous, associated with local gallium impregnation. Such a region would act electrically in series with the single crystal and would presumably have a considerable negative influence on the dielectric properties. However, thermal annealing prior to gold electrodes deposition was found to fully recover the single crystal capacitors and homogenise the gallium profile. The dielectric testing of the STO ultra-thin single crystal capacitors was performed yielding a room temperature dielectric constant of similar to300, as is the case in bulk. Therefore, there was no evidence of a collapse in dielectric constant associated with thin film dimensions.

Progressive loss of ferroelectricity under bipolar pulsed fields and experimental determination of non-switchable polarization in Au/Ba0.5Sr0.5TiO3/SrRuO3 thin-film capacitors

175 nm-thick Ba0.5Sr0.5TiO3 (BST) thin film fabricated by pulsed laser deposition (PLD) technique is found to be a mixture of two distributions of material. We discuss whether these two components are nano-regions of paraelectric and ferroelectric phases, or a bimodal grain-size distribution, or an effect of oxygen vacancy gradient from the electrode interface. The fraction of switchable ferroelectric phase decreases under bipolar pulsed fields, but it recovers after removal of the external fields. The plot of capacitance in decreasing dc voltage (C(Vdown arrow) versus that in increasing dc 61 voltage C(Vup arrow) is a superposition of overlapping of two triangles, in contrast to one well-defined triangle for typical ferroelectric SrBi2Ta2O9 thin films.

Understanding thickness effects in thin film capacitors

Pulsed Laser Deposition (PLD) was used to make Au/(Ba0.5Sr0.5)TiO3/(La0.5Sr0.5) CoO3/MgO thin film capacitor structures. Functional properties were studied with changing BST thickness from similar to1265 nm to similar to63 nm. The dielectric constant was found to decrease, and migration of T-m (the temperature at which the dielectric constant is maximum) to lower temperatures occurred as thickness was reduced. Curie-Weiss plots of the as-obtained dielectric data, indicated that the Curie temperature was also systemmatically progressively depressed. Further, fitting to expressions previously used to describe diffuse phase transitions suggested increased diffuseness in transformation behaviour as film thickness decreased. This paper discusses the care needed in interpreting the observations given above. We make particular distinction between the apparent Curie-temperature derived from Curie-Weiss plots of as-measured data, and the inherent Curie temperature determined after correction for the interfacial capacitance. We demonstrate that while the apparent Curie temperature decreases as thickness decreases, the inherent Curie temperature is thickness independent. Thickness-invariant phase transition behaviour is confirmed from analysis of polarisation loops, and from examination of the temperature dependence of the loss-tangent. We particularly note that correction of data for interfacial capacitance does not alter the position of T-m. We must therefore conclude that the position of T-m is not related simply to phase transformation behaviour in BST thin films.

Maximum of dielectric permittivity caused by structural transition in ferroelectric BaTiO3-SrTiO3 superlattices

We invoke the onset of dislocations along the BaTiO3-SrTiO3 interface as reported by Wunderlich et al. to explain the non-monotonic behaviour of the dielectric permittivity as a function of superlattice periodicity and the less than four-fold in-plane symmetry at the dielectric maximum. At a periodicity of about 10/10, depending on composition and growth mechanism, several groups report a maximum of dielectric permittivity. In addition to that we observe in-plane symmetry less than tetragonal for 10/10 superlattices by HR-XRD, in contrast to initial low-resolution data from Tabata et al. thus challenging the assumption of unrelaxed strain all the way through the superlattice. The aim of this article is to link both effects to the increasing volume fraction of conducting layers close to the interface in series with the superlattice layers.

Switching dynamics in ferroelectric thin films: An experimental survey

We have conducted a broad survey of switching behavior in thin films of a range of ferroelectric materials, including some materials that are not typically considered for FeRAM applications, and are hence less studied. The materials studied include: strontium bismuth tantalate (SBT), barium strontium titanate (BST), lead zicronate titanate (PZT), and potassium nitrate (KNO3). Switching in ferroelectric thin films is typically considered to occur by domain nucleation and growth. We discuss two models of frequency dependence of coercive field, the Ishisbashi-Orihara theory where the limiting step is domain growth and the model of Du and Chen where the limiting step is nucleation. While both models fit the data fairly well the temperature dependence of our results on PZT and BST suggest that the nucleation model of Du and Chen is more appropriate for the experimental results that we have obtained.

Spatially resolved diagnostics on a micro atmospheric pressure plasma jet

Despite enormous potential for technological applications, fundamentals of stable non-equilibrium micro-plasmas at ambient pressure are still only partly understood. Micro-plasma jets are one sub-group of these plasma sources. For an understanding it is particularly important to analyse transport phenomena of energy and particles within and between the core and effluent of the discharge. The complexity of the problem requires the combination and correlation of various highly sophisticated diagnostics yielding different information with an extremely high temporal and spatial resolution. A specially designed rf microscale atmospheric pressure plasma jet (µ-APPJ) provides excellent access for optical diagnostics to the discharge volume and the effluent region. This allows detailed investigations of the discharge dynamics and energy transport mechanisms from the discharge to the effluent. Here we present examples for diagnostics applicable to different regions and combine the results. The diagnostics applied are optical emission spectroscopy (OES) in the visible and ultraviolet and two-photon absorption laser-induced fluorescence spectroscopy. By the latter spatially resolved absolutely calibrated density maps of atomic oxygen have been determined for the effluent. OES yields an insight into energy transport mechanisms from the core into the effluent. The first results of spatially and phase-resolved OES measurements of the discharge dynamics of the core are presented.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.