90 resultados para important memories


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Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide higher density and/or reduced power consumption. One major challenge that impedes the widespread adoption of eDRAM is that they require frequent refreshes potentially reducing the availability of the memory in periods of high activity and also consuming significant amount of power due to such frequent refreshes. Reducing the refresh rate while on one hand can reduce the power overhead, if not performed in a timely manner, can cause some cells to lose their content potentially resulting in memory errors. In this paper, we consider extending the refresh period of gain-cell based dynamic memories beyond the worst-case point of failure, assuming that the resulting errors can be tolerated when the use-cases are in the domain of inherently error-resilient applications. For example, we observe that for various data mining applications, a large number of memory failures can be accepted with tolerable imprecision in output quality. In particular, our results indicate that by allowing as many as 177 errors in a 16 kB memory, the maximum loss in output quality is 11%. We use this failure limit to study the impact of relaxing reliability constraints on memory availability and retention power for different technologies.

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In the United Kingdom (UK) the centenary commemoration of the First World War has been driven by a combination of central government direction (and funding) with a multitude of local and community initiatives, with a particular focus on 4 August 2014; 1 July 2016 (the beginning of the Battle of the Somme) and 11 November 2018. ‘National’ ceremonies on these dates have been and will be supplemented with projects commemorating micro-stories and government-funded opportunities for schoolchildren to visit Great War battlefields, the latter clearly aimed to reinforce a contemporary sense of civic and national obligation and service. This article explores the problematic nature of this approach, together with the issues raised by the multi-national nature of the UK state itself.

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Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

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In this paper, we introduce a statistical data-correction framework that aims at improving the DSP system performance in presence of unreliable memories. The proposed signal processing framework implements best-effort error mitigation for signals that are corrupted by defects in unreliable storage arrays using a statistical correction function extracted from the signal statistics, a data-corruption model, and an application-specific cost function. An application example to communication systems demonstrates the efficacy of the proposed approach.

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The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

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In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

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Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overhead incurred by conventional error correction schemes. In this paper, we exploit the tolerable imprecision of such applications by designing an energy-efficient fault-mitigation scheme for unreliable data memories to meet target yield. The proposed approach uses a bit-shuffling mechanism to isolate faults into bit locations with lower significance. This skews the bit-error distribution towards the low order bits, substantially limiting the output error magnitude. By controlling the granularity of the shuffling, the proposed technique enables trading-off quality for power, area, and timing overhead. Compared to error-correction codes, this can reduce the overhead by as much as 83% in read power, 77% in read access time, and 89% in area, when applied to various data mining applications in 28nm process technology.

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Mesenchymal stromal cells (MSC) have been reported to improve bacterial clearance in pre-clinical models of Acute Respiratory Distress Syndrome (ARDS) and sepsis. The mechanism of this effect is not fully elucidated yet. The primary objective of this study was to investigate the hypothesis that the anti-microbial effect of MSC in vivo depends on their modulation of macrophage phagocytic activity which occurs through mitochondrial transfer. We established that selective depletion of alveolar macrophages (AM) with intranasal (IN) administration of liposomal clodronate resulted in complete abrogation of MSC anti-microbial effect in the in vivo model of E.coli pneumonia. Furthermore, we showed that MSC administration was associated with enhanced AM phagocytosis in vivo. We showed that direct co-culture of MSC with monocyte-derived macrophages (MDMs) enhanced their phagocytic capacity. By fluorescent imaging and flow cytometry we demonstrated extensive mitochondrial transfer from MSC to macrophages which occurred at least partially through TNT-like structures. We also detected that lung macrophages readily acquire MSC mitochondria in vivo, and macrophages which are positive for MSC mitochondria display more pronounced phagocytic activity. Finally, partial inhibition of mitochondrial transfer through blockage of TNT formation by MSC resulted in failure to improve macrophage bioenergetics and complete abrogation of the MSC effect on macrophage phagocytosis in vitro and the anti-microbial effect of MSC in vivo.

Collectively, this work for the first time demonstrates that mitochondrial transfer from MSC to innate immune cells leads to enhancement in phagocytic activity and reveals an important novel mechanism for the anti-microbial effect of MSC in ARDS.

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In Northern Ireland, decades of religious and political unrest led to the marginalization not only of rights but also the experiences and voices of those who identify as Lesbian, Gay, Bisexual, Trans and/or Queer (LGBTQ). The peace process has arguably created space in which sexual minorities can voice their experiences and articulate counter-memories to those that tend to dominate ethno-nationalist commemorations of the conflict. This essay explores two productions of Northern Ireland’s first publicly funded gay theatre company, TheatreofplucK, led by artistic director Niall Rea: D.R.A.G (Divided, Radical and Gorgeous) was first performed in 2011 and explores the personal experiences of a Belfast drag queen in the form of personal testimonial monologue. The forthcoming (November 2015) performed archive installation, Tr<uble, by Shannon Yee, assembles true-life testimonies of the LGBTQ community in Northern Ireland during and after the Troubles. I will explore how performed and performative memories have the potential to ‘queer’ remembrance of the Troubles.

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Memory is thought to be about the past. The past is a problem in conflict transformation. This lecture suggests memory can also be about the future. It introduces the notion of remembering forwards, which is contrasted with remembering backwards. The distinction between these two forms of remembering defines the burden of memory in post-conflict societies generally and specifically in Ireland. In societies emerging out of conflict, where divided memories in part constituted the conflict, social memory privileges remembering backward. Collective and personal memories elide within social memory to perpetuate divided group identities and contested personal narratives. Above all, social memory works to arbitrate the future, by predisposing an extreme memory culture that locks people into the past. Forgetting the past is impossible and undesirable. What is needed in societies emerging out of conflict is to be released from the hold that oppressive and haunting memories have over people. This lecture will suggest that this is found in the idea of remembering forwards. This is not the same as forgetting. It is remembering to cease to remember oppressive and haunting memories. It does not involve non-remembrance but active remembering: remembering to cease to remember the past. While the past lives in us always, remembering forwards assists us in not living in the past. Remembering forwards thus allows us to live in tolerance in the future despite the reality that divided memories endure and live on. The lecture further argues that these enduring divided memories need to be reimagined by the application of truth, tolerance, togetherness and trajectory. The lecture suggests that it is through remembering forwards with truth, tolerance, togetherness and trajectory that people in post-conflict societies can inherit the future despite their divided pasts and live in tolerance in the midst of contested memories.