Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder
Data(s) |
27/07/2015
|
---|---|
Resumo |
<p>The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).</p> |
Identificador |
http://dx.doi.org/10.1109/ISCAS.2015.7168911 http://www.scopus.com/inward/record.url?scp=84946223844&partnerID=8YFLogxK |
Idioma(s) |
eng |
Publicador |
Institute of Electrical and Electronics Engineers Inc. |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Meinerzhagen , P , Bonetti , A , Karakonstantis , G , Roth , C , Giirkaynak , F & Burg , A 2015 , Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder . in Proceedings - IEEE International Symposium on Circuits and Systems . , 7168911 , Institute of Electrical and Electronics Engineers Inc. , pp. 1426-1429 , IEEE International Symposium on Circuits and Systems, ISCAS 2015 , Lisbon , Portugal , 24-27 May . DOI: 10.1109/ISCAS.2015.7168911 |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
Tipo |
contributionToPeriodical |