175 resultados para electrical and electronics engineering


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Thin film Ba0.5Sr0.5TiO3 (BST) capacitors of thickness similar to75 nm to similar to1200 nm, with Au top electrodes and SrRuO 3 (SRO) or (La, Sr)CoO3 (LSCO) bottom electrodes were fabricated using Pulsed Laser Deposition. Implementing the "series capacitor model," bulk and interfacial capacitance properties were extracted as a function of temperature and frequency. 'Bulk' properties demonstrated typical ceramic behaviour, displaying little frequency dependence and a permittivity and loss peak at 250 K and 150 K respectively. The interfacial component was found to be relatively temperature and frequency independent for the LSCO/BST capacitors, but for the SRO/BST configuration the interfacial capacitance demonstrated moderate frequency and little temperature dependence below T similar to 300 K but a relatively strong frequency and temperature dependence above T similar to3 00 K. This was attributed to the thermal activation of a space charge component combined with a thermally independent background. The activation energy for the space charge was found to be E-A similar to 0.6 eV suggesting de-trapping of electrons from shallow level traps associated with a thin interfacial layer of oxygen vacancies, parallel to the electrodes.

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175 nm-thick Ba0.5Sr0.5TiO3 (BST) thin film fabricated by pulsed laser deposition (PLD) technique is found to be a mixture of two distributions of material. We discuss whether these two components are nano-regions of paraelectric and ferroelectric phases, or a bimodal grain-size distribution, or an effect of oxygen vacancy gradient from the electrode interface. The fraction of switchable ferroelectric phase decreases under bipolar pulsed fields, but it recovers after removal of the external fields. The plot of capacitance in decreasing dc voltage (C(Vdown arrow) versus that in increasing dc 61 voltage C(Vup arrow) is a superposition of overlapping of two triangles, in contrast to one well-defined triangle for typical ferroelectric SrBi2Ta2O9 thin films.

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Closed-form expressions for the level crossing rate and average fade duration of a kappa–mu distributed fading signal envelope are presented. The proposed equations are validated by reduction to known Rice, Rayleigh and Nakagami-m special cases. They are also compared with measured data obtained from field trials analysing human body to body radio channels and shown to provide good agreement.

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Power deposition in the head of a user wearing metal-framed spectacles was calculated with a 450 MHz personal radio transmitting in close proximity. Peak tissue SAR in the head depended on lens shape whether circular half-rim or rectangular with 70 and 174% increases, respectively, compared to the spectacle-free case. However, localised screening occurred with square frames, with a 40% reduction of peak SAR in the eye closest to the antenna.

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A novel, fast automatic motion segmentation approach is presented. It differs from conventional pixel or edge based motion segmentation approaches in that the proposed method uses labelled regions (facets) to segment various video objects from the background. Facets are clustered into objects based on their motion and proximity details using Bayesian logic. Because the number of facets is usually much lower than the number of edges and points, using facets can greatly reduce the computational complexity of motion segmentation. The proposed method can tackle efficiently the complexity of video object motion tracking, and offers potential for real-time content-based video annotation.

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An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

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Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

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A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

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A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.