106 resultados para IP masquerading


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SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

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A rapid design methodology for biorthogonal wavelet transform cores has been developed based on a generic, scaleable architecture for wavelet filters. The architecture offers efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation in a MAC-based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet system is typically less than a day. The silicon cores produced are comparable in area and performance to hand-crafted designs, The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

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This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

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The identification and classification of network traffic and protocols is a vital step in many quality of service and security systems. Traffic classification strategies must evolve, alongside the protocols utilising the Internet, to overcome the use of ephemeral or masquerading port numbers and transport layer encryption. This research expands the concept of using machine learning on the initial statistics of flow of packets to determine its underlying protocol. Recognising the need for efficient training/retraining of a classifier and the requirement for fast classification, the authors investigate a new application of k-means clustering referred to as 'two-way' classification. The 'two-way' classification uniquely analyses a bidirectional flow as two unidirectional flows and is shown, through experiments on real network traffic, to improve classification accuracy by as much as 18% when measured against similar proposals. It achieves this accuracy while generating fewer clusters, that is, fewer comparisons are needed to classify a flow. A 'two-way' classification offers a new way to improve accuracy and efficiency of machine learning statistical classifiers while still maintaining the fast training times associated with the k-means.

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Haptic information originates from a different human sense (touch), therefore the quality of service (QoS) required to supporthaptic traffic is significantly different from that used to support conventional real-time traffic such as voice or video. Each type ofnetwork impairment has different (and severe) impacts on the user’s haptic experience. There has been no specific provision of QoSparameters for haptic interaction. Previous research into distributed haptic virtual environments (DHVEs) have concentrated onsynchronization of positions (haptic device or virtual objects), and are based on client-server architectures.We present a new peerto-peer DHVE architecture that further extends this to enable force interactions between two users whereby force data are sent tothe remote peer in addition to positional information. The work presented involves both simulation and practical experimentationwhere multimodal data is transmitted over a QoS-enabled IP network. Both forms of experiment produce consistent results whichshow that the use of specific QoS classes for haptic traffic will reduce network delay and jitter, leading to improvements in users’haptic experiences with these types of applications.

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Synchronous islanded operation involves continuously holding an islanded power network in virtual synchronism with the main power system to aid paralleling and avoid potentially damaging out-of-synchronism reclosure. This requires phase control of the generators in the island and the transmission of a reference signal from a secure location on the main power system. Global positioning system (GPS) time-synchronized phasor measurements transmitted via an Internet protocol (IP) are used for the reference signal. However, while offering low cost and a readily available solution for distribution networks, IP communications have variable latency and are susceptible to packet loss, which can make time-critical control applications difficult. This paper investigates the ability of the phase-control system to tolerate communications latency. Phasor measurement conditioning algorithms that can tolerate latency are used in the phase-control loop of a 50-kVA diesel generator. © 2010 IEEE.

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PURPOSE:
To investigate endothelin 1 (Et1)-dependent Ca(2+)-signaling at the cellular and subcellular levels in retinal arteriolar myocytes.
METHODS:
Et1 responses were imaged from Fluo-4-loaded smooth muscle in isolated segments of rat retinal arteriole using confocal laser microscopy.
RESULTS:
Basal [Ca(2+)](i), subcellular Ca(2+)-sparks, and cellular Ca(2+)-oscillations were all increased during exposure to Et1 (10 nM). Ca(2+)-spark frequency was also increased by 90% by 10 nM Et1. The increase in oscillation frequency was concentration dependent and was inhibited by the EtA receptor (Et(A)R) blocker BQ123 but not by the EtB receptor antagonist BQ788. Stimulation of Ca(2+)-oscillations by Et1 was inhibited by a phospholipase C blocker (U73122; 10 µM), two inhibitors of inositol 1,4,5-trisphosphate receptors (IP(3)Rs), xestospongin C (10 µM), 2-aminoethoxydiphenyl borate (100 µM), and tetracaine (100 µM), a blocker of ryanodine receptors (RyRs).
CONCLUSIONS:
Et1 stimulates Ca(2+)-sparks and oscillations through Et(A)Rs. The underlying mechanism involves the activation of phospholipase C and both IP(3)Rs and RyRs, suggesting crosstalk between these Ca(2+)-release channels. These findings suggest that phasic Ca(2+)-oscillations play an important role in the smooth muscle response to Et1 within the retinal microvasculature and support an excitatory, proconstrictor role for Ca(2+)-sparks in these vessels.

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Sendai virus (SeV) is a murine respiratory virus of considerable interest as a gene therapy or vaccine vector, as it is considered nonpathogenic in humans. However, little is known about its interaction with the human respiratory tract. To address this, we developed a model of respiratory virus infection based on well-differentiated primary pediatric bronchial epithelial cells (WD-PBECs). These physiologically authentic cultures are comprised of polarized pseudostratified multilayered epithelium containing ciliated, goblet, and basal cells and intact tight junctions. To facilitate our studies, we rescued a replication-competent recombinant SeV expressing enhanced green fluorescent protein (rSeV/eGFP). rSeV/eGFP infected WD-PBECs efficiently and progressively and was restricted to ciliated and nonciliated cells, not goblet cells, on the apical surface. Considerable cytopathology was evident in the rSeV/eGFP-infected cultures postinfection. This manifested itself by ciliostasis, cell sloughing, apoptosis, and extensive degeneration of WD-PBEC cultures. Syncytia were also evident, along with significant basolateral secretion of proinflammatory chemokines, including IP-10, RANTES, tumor necrosis factor (TNF)-related apoptosis-inducing ligand (TRAIL), interleukin 6 (IL-6), and IL-8. Such deleterious responses are difficult to reconcile with a lack of pathogenesis in humans and suggest that caution may be required in exploiting replication-competent SeV as a vaccine vector. Alternatively, such robust responses might constitute appropriate normal host responses to viral infection and be a prerequisite for the induction of efficient immune responses.

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A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.

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Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

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Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

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A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

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Recent thinking on open innovation and the knowledge-based economy have stressed the importance of external knowledge sources in stimulating innovation. Policy-makers have recognised this, establishing publicly funded Centres of R&D Excellence with the objective of stimulating industry–science links and localised innovation spillovers. Here, we examine the contrasting IP management practices of a group of 18 university- and company-based R&D centres supported by the same regional programme. Our analysis covers all but one of the Centres supported by the programme and suggests marked contrasts between the IP strategies of the university-based and company-based centres. This suggests the potential for very different types of knowledge spillovers from publicly funded R&D centres based in different types of organisations, and a range of alternative policy approaches to the future funding of R&D centres depending on policy-makers’ objectives.

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GYY4137 (morpholin-4-ium-4-methoxyphenyl(morpholino) phosphinodithioate) is a slow-releasing hydrogen sulfide (H2S) donor. Administration of GYY4137 (50 mg/kg, iv) to anesthetized rats 10 min after lipopolysaccharide (LPS; 4 mg/kg, iv) decreased the slowly developing hypotension. GYY4137 inhibited LPS-induced TNF-alpha production in rat blood and reduced the LPS-evoked rise in NF-kappa B;B activation, inducible nitric oxide synthase/cyclooxygenase-2 expression, and generation of PGE(2) and nitrate/nitrite in RAW 264.7 macrophages. GYY4137 (50 mg/kg, ip) administered to conscious rats 1 or 2 h after (but not 1 h before) LPS decreased the subsequent (4 h) rise in plasma proinflammatory cytokines (TNF-alpha, IL-1 beta, IL-6), nitrite/nitrate, C-reactive protein, and L-selectin. GYY4137 administration also decreased the LPS-evoked increase in lung myeloperoxidase activity, increased plasma concentration of the anti-inflammatory cytokine IL-10, and decreased tissue damage as determined histologically and by measurement of plasma creatinine and alanine aminotransferase activity. Tune-expired GYY4137 (50 mg/kg, ip) did not affect the LPS-induced rise in plasma TNF-alpha or lung myeloperoxidase activity. GYY4137 also decreased the LPS-mediated upregulation of liver transcription factors (NF-kappa B and STAT-3). These results suggest ail anti-inflammatory effect of GYY4137. The possibility that GYY4137 and other slow-releasing H2S donors exert anti-inflammatory activity in other models of inflammation and in humans warrants further study. (C) 2009 Elsevier Inc. All rights reserved.

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Hydrogen sulfide (H2S) is synthesized in the body from L-Cysteine by several enzymes including cystathionine-gamma-lyase (CSE). To date, there is little information about the potential role of H2S in inflammation. We have now investigated the part played by H2S in endotoxin-induced inflammation in the mouse. E. coli lipopolysaccharide (LPS) administration produced a dose (10 and 20 mg/kg ip)- and time (6 and 24 h)-dependent increase in plasma H2S concentration. LPS (10 mg/kg ip, 6 h) increased plasma H2S concentration from 34.1 +/- 0.7 mu M to 40.9 +/- 0.6 mu M (n=6, P