Power Efficient DSP Datapath Configuration Methodology for FPGA
| Data(s) |
01/09/2008
|
|---|---|
| Identificador |
http://dx.doi.org/10.1109/FPL.2008.4629997 http://www.scopus.com/inward/record.url?scp=54949085083&partnerID=8YFLogxK |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
McKeown , M , Woods , R & McAllister , J 2008 , Power Efficient DSP Datapath Configuration Methodology for FPGA . in 2008 International Conference on Field Programmable Logic and Applications. Proceedings . pp. 515-518 , 2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08) , Heidelberg , Germany , 8-10 September . DOI: 10.1109/FPL.2008.4629997 |
| Tipo |
contributionToPeriodical |
| Resumo |
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures. |
