Cartographic veracity in medieval mapping: analyzing geographical variation in the Gough Map of Great Britain

This article explores statistical approaches for assessing the relative accuracy of medieval mapping. It focuses on one particular map, the Gough Map of Great Britain. This is an early and remarkable example of a medieval “national” map covering Plantagenet Britain. Conventionally dated to c. 1360, the map shows the position of places in and coastal outline of Great Britain to a considerable degree of spatial accuracy. In this article, aspects of the map's content are subjected to a systematic analysis to identify geographical variations in the map's veracity, or truthfulness. It thus contributes to debates among historical geographers and cartographic historians on the nature of medieval maps and mapping and, in particular, questions of their distortion of geographic space. Based on a newly developed digital version of the Gough Map, several regression-based approaches are used here to explore the degree and nature of spatial distortion in the Gough Map. This demonstrates that not only are there marked variations in the positional accuracy of places shown on the map between regions (i.e., England, Scotland, and Wales), but there are also fine-scale geographical variations in the spatial accuracy of the map within these regions. The article concludes by suggesting that the map was constructed using a range of sources, and that the Gough Map is a composite of multiscale representations of places in Great Britain. The article details a set of approaches that could be transferred to other contexts and add value to historic maps by enhancing understanding of their contents.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.