Design of quantum-dot cellular automata circuits using cut-set retiming

As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCAs unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCAs unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.

An On Demand Queue Management Architecture for a Programmable Traffic Manager

A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Functional management of ankle sprains: what volume and intensity of walking is undertaken in the first week postinjury:what volume and intensity of walking is undertaken in the first week postinjury

BACKGROUND: Acute ankle sprains are usually managed functionally, with advice to undertake progressive weight-bearing and walking. Mechanical loading is an important modular of tissue repair; therefore, the clinical effectiveness of walking after ankle sprain may be dose dependent. The intensity, magnitude and duration of load associated with current functional treatments for ankle sprain are unclear.

AIM: To describe physical activity (PA) in the first week after ankle sprain and to compare results with a healthy control group.

METHODS: Participants (16-65 years) with an acute ankle sprain were randomised into two groups (standard or exercise). Both groups were advised to apply ice and compression, and walk within the limits of pain. The exercise group undertook additional therapeutic exercises. PA was measured using an activPAL accelerometer, worn for 7 days after injury. Comparisons were made with a non-injured control group.

RESULTS: The standard group were significantly less active (1.2 ± 0.4 h activity/day; 5621 ± 2294 steps/day) than the exercise (1.7 ± 0 .7 h/day, p=0.04; 7886 ± 3075 steps/day, p=0.03) and non-injured control groups (1.7 ± 0.4 h/day, p=0.02; 8844 ± 2185 steps/day, p=0.002). Also, compared with the non-injured control group, the standard and exercise groups spent less time in moderate (38.3 ± 12.7 min/day vs 14.5 ± 11.4 min/day, p=0.001 and 22.5 ± 15.9 min/day, p=0.003) and high-intensity activity (4.1 ± 6.9 min/day vs 0.1 ± 0.1 min/day, p=0.001 and 0.62 ± 1.0 min/day p=0.005).

CONCLUSION: PA patterns are reduced in the first week after ankle sprain, which is partly ameliorated with addition of therapeutic exercises. This study represents the first step towards developing evidence-based walking prescription after acute ankle sprain.

Rapid design of application specific FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterized commutator and processor blocks are cascaded to implement the computations required in many important FFT signal flow graphs. In addition, it is shown how the use of a digital serial data organization can be used to produce systems that offer 100% processor utilization along with reductions in storage requirements. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with ones created using manual methods but with significant reductions in design times.

Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

Rapid silicon design of discrete orthonormal wavelet transforms based algorithms

A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.

Synthesizable FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

A low-cost solution for the restoration of femoral head centre during total hip arthroplasty

Restoration of joint centre during total hip arthroplasty is critical. While computer-aided navigation can improve accuracy during total hip arthroplasty, its expense makes it inaccessible to the majority of surgeons. This article evaluates the use, in the laboratory, of a calliper with a simple computer application to measure changes in femoral head centres during total hip arthroplasty. The computer application was designed using Microsoft Excel and used calliper measurements taken pre- and post-femoral head resection to predict the change in head centre in terms of offset and vertical height between the femoral head and newly inserted prosthesis. Its accuracy was assessed using a coordinate measuring machine to compare changes in preoperative and post-operative head centre when simulating stem insertion on 10 sawbone femurs. A femoral stem with a modular neck was used, which meant nine possible head centre configurations were available for each femur, giving 90 results. The results show that using this technique during a simulated total hip arthroplasty, it was possible to restore femoral head centre to within 6?mm for offset (mean 1.67?±?1.16?mm) and vertical height (mean 2.14?±?1.51?mm). It is intended that this low-cost technique be extended to inform the surgeon of a best-fit solution in terms of neck length and neck type for a specific prosthesis.

Modification of Fluorescent Photoinduced Electron Transfer (PET) Sensors/Switches To Produce Molecular Photo-Ionic Triode Action

The fluorophore-spacer₁-receptor₁-spacer₂-receptor₂ system (where receptor₂ alone is photoredox-inactive) shows ionically tunable proton-induced fluorescence off-on switching, which is reminiscent of thermionic triode behavior. This also represents a new extension to modular switch systems based on photoinduced electron transfer (PET) towards the emulation of analogue electronic devices.

A spectral synthesis code for rapid modelling of supernovae

We present TARDIS-an open-source code for rapid spectral modelling of supernovae (SNe). Our goal is to develop a tool that is sufficiently fast to allow exploration of the complex parameter spaces of models for SN ejecta. This can be used to analyse the growing number of highquality SN spectra being obtained by transient surveys. The code uses Monte Carlo methods to obtain a self-consistent description of the plasma state and to compute a synthetic spectrum. It has a modular design to facilitate the implementation of a range of physical approximations that can be compared to assess both accuracy and computational expediency. This will allow users to choose a level of sophistication appropriate for their application. Here, we describe the operation of the code and make comparisons with alternative radiative transfer codes of differing levels of complexity (SYN++, PYTHON and ARTIS). We then explore the consequence of adopting simple prescriptions for the calculation of atomic excitation, focusing on four species of relevance to Type Ia SN spectra-Si II, SII, MgII and Ca II. We also investigate the influence of three methods for treating line interactions on our synthetic spectra and the need for accurate radiative rate estimates in our scheme.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

High-Speed Fully Homomorphic Encryption Over the Integers

A fully homomorphic encryption (FHE) scheme is envisioned as a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrary evaluation of a ciphertext without revealing the plaintext. However, existing FHE implementations remain impractical due to very high time and resource costs. To the authors’ knowledge, this paper presents the first hardware implementation of a full encryption primitive for FHE over the integers using FPGA technology. A large-integer multiplier architecture utilising Integer-FFT multiplication is proposed, and a large-integer Barrett modular reduction module is designed incorporating the proposed multiplier. The encryption primitive used in the integer-based FHE scheme is designed employing the proposed multiplier and modular reduction modules. The designs are verified using the Xilinx Virtex-7 FPGA platform. Experimental results show that a speed improvement factor of up to 44 is achievable for the hardware implementation of the FHE encryption scheme when compared to its corresponding software implementation. Moreover, performance analysis shows further speed improvements of the integer-based FHE encryption primitives may still be possible, for example through further optimisations or by targeting an ASIC platform.

Synthesisable FFT cores

Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% processor utilisation with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

Characterizing wear processes on orthopaedic materials using scanning probe microscopy

The operational lifetime of hip replacement prostheses can be severely limited due to the occurrence of excessive wear at the load-bearing interfaces. The aim of this study was to investigate how the surface topography of articulating counterfaces evolves over the duration of a laboratory wear run. It was observed that modular stainless steel femoral heads wearing against ultrahigh molecular weight polyethylene (UHMWPE) can themselves be subject to wearing. A comparison with retrieved in vivo-aged femoral heads shows many topographical similarities: in a qualitative sense, scratching and pitting are evident on laboratory and in vivo-worn femoral heads; quantitatively, roughness comparisons between the new and worn devices are seen to increase typically by a factor of 4 after laboratory wearing. The observations suggest that a particular wear mode, namely third-body wear, is responsible for the increased roughness. It is conjectured that third bodies might arise through surface fatigue wear on the metal counterface, Wear debris is also observed to have been generated from the polymer surface, creating rounded debris with sizes predominantly in the range 0.4-0.8 microns: dimensions that are comparable to values previously reported for in vivo generated debris.